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參數(shù)資料
| 型號： | LTC1052CSW#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP CHOP-STBL LONOIS16SOIC |
| 標準包裝： | 47 |
| 系列： | LTCMOS™ |
| 放大器類型： | 斷路器（零漂移） |
| 電路數(shù)： | 1 |
| 轉(zhuǎn)換速率： | 4 V/µs |
| 增益帶寬積： | 1.2MHz |
| 電流 - 輸入偏壓： | 1pA |
| 電壓 - 輸入偏移： | 0.5µV |
| 電流 - 電源： | 1.7mA |
| 電壓 - 電源，單路/雙路(±)： | 4.75 V ~ 16 V，±2.38 V ~ 8 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SO |
| 包裝： | 管件 |
LTC1052/LTC7652
11
1052fa
PACKAGE-INDUCED OFFSET VOLTAGE
Since the LTC1052 is constantly fixing its own offset, it
may be asked why there is any error at all, even under
transient temperature conditions. The answer is simple.
The LTC1052 can only fix offsets inside its own nulling
loop. There are many thermal junctions outside this loop
that cannot be distinguished from legitimate signals.
Some have been discussed previously, but the package
thermal EMF effects are an important source of errors.
Notice the difference in the thermal response curves of
Figure 4. This can only be attributed to the package since
everything else is identical. In fact, the VOS specification is
set by the package-induced warm-up drift, not by the
LTC1052. TO-99 metal cans exhibit the worst warm-up
drift and Linear Technology sample tests TO-99 lots to
minimize this problem.
Two things make 100% screening costly: (1) The extreme
precision required on the LTC1052 and (2) the thermal
time constant of the package is 0.5 to 3 minutes, depend-
ing on package type. The first precludes the use of auto-
matic handling equipment and the second takes a long
time. Bench test equipment is available to 100% test for
warmed-up drift if offsets of less than ±5V are required.
APPLICATIO S I FOR ATIO
WU
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Figure 5. DC to 1Hz (Test Circuit TC3)
1V
#1 COVERED
#1 UNCOVERED
#2 UNCOVERED
20 SEC
CLOCK
The LTC1052 has an internal clock, setting the nominal
sampling frequency at 330Hz. On 8-pin devices, there is
no way to control the clock externally. In some applica-
tions it may be desirable to control the sampling clock and
this is the function of the 14-pin device.
CLK IN, CLK OUT and INT/EXT are provided to accomplish
this. With no external connection, an internal pull-up holds
INT/EXT at the V+ supply and the 14-pin device self-
oscillates at 330Hz. In this mode there is a signal on the
CLK IN pin of 660Hz (2 times sampling frequency) with a
30% duty cycle. A divide-by-two drives the CLK OUT pin
and sets the sampling frequency.
To use an external clock, connect INT/EXT to V– and the
external clock to CLK IN. The logic threshold of CLK IN is
2.5V below the positive supply; this allows CMOS logic to
drive it directly with logic supplies of V+ and ground. CLK
IN can be driven from V+ to V– if desired. The duty cycle of
the external clock is not particularly critical but should be
kept between 30% and 60%.
Capacitance between CLK IN and CLK OUT (pins 13 and
12) can cause the divide-by-two circuit to malfunction. To
avoid this, keep this capacitance below 5pF.
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