參數(shù)資料
型號: LTC1052CSW#PBF
廠商: Linear Technology
文件頁數(shù): 2/24頁
文件大?。?/td> 0K
描述: IC OPAMP CHOP-STBL LONOIS16SOIC
標(biāo)準(zhǔn)包裝: 47
系列: LTCMOS™
放大器類型: 斷路器(零漂移)
電路數(shù): 1
轉(zhuǎn)換速率: 4 V/µs
增益帶寬積: 1.2MHz
電流 - 輸入偏壓: 1pA
電壓 - 輸入偏移: 0.5µV
電流 - 電源: 1.7mA
電壓 - 電源,單路/雙路(±): 4.75 V ~ 16 V,±2.38 V ~ 8 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 16-SO
包裝: 管件
LTC1052/LTC7652
10
1052fa
APPLICATIO S I FOR ATIO
WU
UU
When all of these errors are considered, it may seem
impossible to take advantage of the extremely low drift
specifications of the LTC1052. To show that this is not the
case, examine the temperature test circuit of Figure 3. The
lead lengths of the resistors connected to the amplifier’s
inputs are identical. The thermal capacity and thermal
resistance each input sees is balanced because of the
symmetrical connection of resistors and their identical
size. Thermal EMF-induced shifts are equal in phase and
amplitude, thus cancellation occurs.
Figure 4 shows the response of this circuit under
temperature transient conditions. Metal film resistors and
an 8-pin DIP socket were used. Care was taken in the
construction to thermally balance the inputs to the
amplifier. The units were placed in an oven and allowed to
stabilize at 25°C. The recording was started and after
100 seconds the oven, preset to 125°C, was switched on.
The test was first performed on an 8-pin plastic package
and then was repeated for a TO-5 package plugged into the
same test board. It is significant that the change in VOS,
even under these severe thermal transient conditions,
is quite good. As temperature stabilizes, note that the
steady-state change of VOS is well within the maximum
±0.05V/°C drift specification.
Very slight air currents can still affect even this
arrangement. Figure 5 shows strip charts of output noise
both with the circuit covered and with no cover in “still” air.
This data illustrates why it is often prudent to enclose the
LTC1052 and its attendant components inside some form
of thermal baffle.
Figure 3. Offset Drift Test Circuit
Figure 4. Transient Response of Offset Drift Test Circuit with 100°C Temperature Step
0 MIN
25 MIN
20 MIN
5 MIN
10
0
10
OVEN SWITCHED
ON (25°C)
OVEN STABILIZED
AT 12 MIN
100 SECONDS/IN
OFFSET
VOLTAGE,
V
OS
(10
V/DIV)
25°C TO 125°C
PLASTIC
25°C TO 125°C
METAL CAN
±0.05V/°C
0.1F
50k
3
2
7
6
8
4
1
VOS 1000
5V
LTC1052/7652 AI04
100
50k
–5V
0.1F
LTC1052
+
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