參數(shù)資料
型號(hào)： LTAEZ
廠商： Linear Integrated Systems
英文描述： Differential Input 16-Bit No Latency DS ADC
中文描述： 差分輸入16位ADC的無(wú)延遲局副局長(zhǎng)
文件頁(yè)數(shù)： 6/28頁(yè)
文件大?。?/td> 298K
代理商： LTAEZ
LTC2433-1
6
24331fa
V
CC
(Pin 1):
Positive Supply Voltage. Bypass to GND with
a 10
μ
F tantalum capacitor in parallel with 0.1
μ
F ceramic
capacitor as close to the part as possible.
REF
+
(Pin 2), REF
–
(Pin 3):
Differential Reference Input.
The voltage on these pins can have any value between GND
and V
CC
as long as the reference positive input, REF
+
, is
maintained more positive than the reference negative
input, REF
–
, by at least 0.1V.
IN
+
(Pin 4), IN
–
(Pin 5):
Differential Analog Input. The
voltage on these analog inputs can have any value between
GND and V
CC
. Within these limits the converter bipolar
input range (V
IN
= IN
+
– IN
–
) extends from –0.5 (V
REF
)
to 0.5 (V
REF
). Outside this input range the converter
produces unique overrange and underrange output codes.
GND (Pin 6):
Ground. Connect this pin to a ground plane
through a low impedance connection.
CS (Pin 7):
Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
SDO (Pin 8):
Three-State Digital Output. During the Data
Output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = V
CC
) the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin is used as the conversion status output.
The conversion status can be observed by pulling CS LOW.
SCK (Pin 9):
Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as digital input for the external serial interface
clock during the Data Output period. A weak internal pull-
up is automatically activated in Internal Serial Clock Op-
eration mode. The Serial Clock Operation mode is deter-
mined by the logic level applied to the SCK pin at power up
or during the most recent falling edge of CS.
F
O
(Pin 10):
Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. When the F
O
pin is connected to GND (F
O
= 0V), the
converter uses its internal oscillator and rejects 50Hz and
60Hz simultaneously. When F
O
is driven by an external
clock signal with a frequency f
EOSC
, the converter uses this
signal as its system clock and the digital filter has 87dB
minimum rejection in the range f
EOSC
/2560
±
14% and
110dB minimum rejection at f
EOSC
/2560
±
4%.
PIU
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