參數(shù)資料
型號(hào)： LT6559CUD#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 16/16頁(yè)
文件大小： 0K
描述： IC AMP VIDEO TRPL 16-QFN
標(biāo)準(zhǔn)包裝： 2,500
應(yīng)用： 通用
電路數(shù)： 3
-3db帶寬： 300MHz
轉(zhuǎn)換速率： 800 V/µs
電流 - 電源： 4.6mA
電流 - 輸出 / 通道： 100mA
電壓 - 電源，單路/雙路(±)： 4 V ~ 12 V，±2 V ~ 6 V
安裝類型： 表面貼裝
封裝/外殼： 16-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 16-QFN-EP（3x3）
包裝： 帶卷 (TR)
LT6559
9
6559f
APPLICATIONS INFORMATION
internal capacitance. At a gain of 2 with 301Ω feedback
and gain resistors and ±5V supplies, the output slew rate
is typically 800V/s. Larger feedback resistors will reduce
the slew rate as will lower supply voltages.
Enable/Disable
Each amplier of the LT6559 has a unique high imped-
ance, zero supply current mode which is controlled by its
own
EN pin. These ampliers are designed to operate with
CMOS logic; the ampliers draw 0.1A of current when
these pins are high or oated. To activate each amplier,
its
EN pin is normally pulled to a logic low. However, sup-
ply current will vary as the voltage between the V+ supply
and
EN is varied. As seen in Figure 1, +IS does vary with
(V+ – VEN), particularly when the voltage difference is less
than 3V. For normal operation, it is important to keep the
EN pin at least 3V below the V+ supply. If a V+ of less than
3V is used, for the amplier to remain enabled at all times
the
EN pin should be tied to the V– supply. The enable pin
current is approximately 30A when activated. If using
CMOS open-drain logic, an external 1k pull-up resistor is
recommended to ensure that the LT6559 remains disabled
regardless of any CMOS drain-leakage currents.
Differential Input Signal Swing
To avoid any breakdown condition on the input transis-
tors, the differential input swing must be limited to ±5V.
In normal operation, the differential voltage between the
input pins is small, so the ±5V limit is not an issue. In
the disabled mode however, the differential swing can be
the same as the input swing, and there is a risk of device
breakdown if the input voltage range has not been properly
considered.
V + – VEN (V)
0
+I
S
(mA)
0.5
1.5
2.0
2.5
5.0
3.5
2
4
5
6559 F01
1.0
4.0
4.5
3.0
1
3
6
7
TA = 25°C
V + = 5V
V – = – 5V
V – = 0V
Figure 1. +IS vs (V
+ – VEN)
The enable/disable times are very fast when driven from
standard 5V CMOS logic. Each amplier enables in about
30ns (50% point to 50% point) while operating on ±5V
supplies (Figure 2). Likewise, the disable time is approxi-
mately 40ns (50% point to 50% point) (Figure 3).
Figure 2. Amplier Enable Time, AV = 2
Figure 3. Amplier Disable Time, AV = 2
2V
0V
5V
0V
OUTPUT
6559 F02
VS = ±5V
VIN = 1V
RF = 301
RG = 301
RL = 100
EN
6559 F03
VS = ±5V
VIN = 1V
RF = 301
RG = 301
RL = 100
2V
0V
5V
0V
OUTPUT
EN
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