參數(shù)資料
型號(hào): LT6402IUD-20#PBF
廠商: Linear Technology
文件頁(yè)數(shù): 5/16頁(yè)
文件大?。?/td> 0K
描述: IC DIFF AMP/ADC DRVR 16-QFN
標(biāo)準(zhǔn)包裝: 121
放大器類(lèi)型: 差分
電路數(shù): 2
輸出類(lèi)型: 差分
轉(zhuǎn)換速率: 400 V/µs
-3db帶寬: 300MHz
電流 - 輸入偏壓: 5µA
電壓 - 輸入偏移: 1000µV
電流 - 電源: 30mA
電流 - 輸出 / 通道: 35mA
電壓 - 電源,單路/雙路(±): 4 V ~ 5.5 V,±2 V ~ 2.5 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 16-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 16-QFN-EP(3x3)
包裝: 管件
13
640220fa
LT6402-20
APPLICATIO S I FOR ATIO
WU
U
solution of 14pF from each ltered output to ground plus
a 14pF capacitor between the ltered outputs would also
halve the lter bandwidth (Figure 7).
Bandpass ltering is also easily implemented with just a
few external components. An additional 560pF and 62nH,
each added differentially between +OUTFILTERED and
–OUTFILTERED creates a bandpass lter with a 26MHz
center frequency, –3dB points of 23MHz and 30MHz, and
1.6dB of insertion loss (Figure 8).
Output Common Mode Adjustment
The LT6402-20’s output common mode voltage is set by
the VOCM pin. It is a high-impedance input, capable of
setting the output common mode voltage anywhere in
a range from 1.1V to 3.6V. Bandwidth of the VOCM pin is
typically 200MHz, so for applications where the VOCM pin
is tied to a DC bias voltage, a 0.1F capacitor at this pin is
recommended. For best distortion performance, the voltage
at the VOCM pin should be between 1.8V and 2.6V.
When interfacing with most ADCs, there is generally a
VOCM output pin that is at about half of the supply voltage
of the ADC. For 5V ADCs such as the LTC17XX family, this
VOCM output pin should be connected directly (with the
addition of a 0.1F capacitor) to the input VOCM pin of the
LT6402-20. For 3V ADCs such as the LTC22XX families,
the LT6402-20 will function properly using the 1.65V from
the ADC’s VCM reference pin, but improved Spurious Free
Dynamic Range (SFDR) and distortion performance can
be achieved by level-shifting the LTC22XX’s VCM reference
voltage up to at least 1.8V. This can be accomplished as
shown in Figure 9 by using a resistor divider between the
LTC22XX’s VCM output pin and VCC and then bypassing
the LT6402-20’s VOCM pin with a 0.1F capacitor. For a
common mode voltage above 1.9V, AC coupling capacitors
are recommended between the LT6402-20 and LTC22XX
ADCs because of the input voltage range constraints of
the ADC.
Large Output Voltage Swings
The LT6402-20 has been designed to provide the
3.2VP-P output swing needed by the LTC1748 family
of 14-bit low-noise ADCs. This additional output swing
improves system SNR by up to 4dB.
Input Bias Voltage and Bias Current
The input pins of the LT6402-20 are internally biased to
the voltage applied to the VOCM pin. No external biasing
resistors are needed, even for AC-coupled operation. The
input bias current is determined by the voltage difference
between the input common mode voltage and the VOCM
pin (which sets the output common mode voltage). For
example, if the inputs are tied to 2.5V with the VOCM pin
at 2.2V, then a total input bias current of 1mA will ow
into the LT6402-20’s +INA and +INB pins. Furthermore,
an additional input bias current totaling 1mA will ow into
the –INA and –INB inputs.
Application (Demo) Boards
The DC954A Demo Board has been created for stand-alone
evaluation of the LT6402-20 with either single-ended or
differential input and output signals. As shown, it accepts
a single-ended input and produces a single-ended output
so that the LT6402-20 can be evaluated using standard
laboratory test equipment. For more information on this
Demo Board, please refer to the layout and schematic
diagrams found later in this data sheet.
There are also additional demo boards available that
combine the LT6402-20 with a variety of different Linear
Technology ADCs. Please contact the factory for more
information on these demo boards.
6402 F9
IF IN
LT6402-20
–INA
–INB
VOCM
2
31
6
7
1
2
+INB
+INA
14
13
15
121
16
10
10
LTC22xx
0.1
F
0.1
F
+OUTFILTERED
–OUTFILTERED
AIN+
AIN
4.02k
11k
1.9V
1.5V
3V
VCM
Figure 9. Level Shifting 3V ADC VCM Voltage for
Improved SFDR
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