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參數(shù)資料
| 型號： | LT6402IUD-20#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DIFF AMP/ADC DRVR 16-QFN |
| 標(biāo)準(zhǔn)包裝： | 121 |
| 放大器類型： | 差分 |
| 電路數(shù)： | 2 |
| 輸出類型： | 差分 |
| 轉(zhuǎn)換速率： | 400 V/µs |
| -3db帶寬： | 300MHz |
| 電流 - 輸入偏壓： | 5µA |
| 電壓 - 輸入偏移： | 1000µV |
| 電流 - 電源： | 30mA |
| 電流 - 輸出 / 通道： | 35mA |
| 電壓 - 電源，單路/雙路(±)： | 4 V ~ 5.5 V，±2 V ~ 2.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 16-QFN-EP（3x3） |
| 包裝： | 管件 |
9
640220fa
LT6402-20
VOCM (Pin 2): This pin sets the output common mode
voltage. Without additional biasing, both inputs bias to
this voltage as well. This input is high impedance.
VCCA, VCCB, VCCC (Pins 3, 10, 1): Positive Power Supply
(Normally Tied to 5V). All three pins must be tied to the
same voltage. Bypass each pin with 1000pF and 0.1F
capacitors as close to the package as possible. Split
supplies are possible as long as the voltage between VCC
and VEE is 5V.
VEEA, VEEB, VEEC (Pins 4, 9, 12): Negative Power Supply
(Normally Tied to Ground). All three pins must be tied to
the same voltage. Split supplies are possible as long as
the voltage between VCC and VEE is 5V. If these pins are
not tied to ground, bypass each pin with 1000pF and 0.1F
capacitors as close to the package as possible.
+OUT, –OUT (Pins 5, 8): Outputs (Unltered). These
pins are high bandwidth, low-impedance outputs. The DC
output voltage at these pins is set to the voltage applied
at VOCM.
+OUTFILTERED, –OUTFILTERED (Pins 6, 7): Filtered
Outputs. These pins add a series 50Ω resistor from the
unltered outputs and three 14pF capacitors. Each output
has 14pF to VEE, plus an additional 14pF between each pin
(See the Block Diagram). This lter has a –3dB bandwidth
of 75MHz.
ENABLE (Pin 11): This pin is a TTL logic input referenced
to the VEEC pin. If low, the LT6402 is enabled and draws
typically 30mA of supply current. If high, the LT6402 is
disabled and draws typically 250A.
+INA, +INB (Pins 15, 16): Positive Inputs. These pins are
normally tied together. These inputs may be DC- or AC-
coupled. If the inputs are AC-coupled, they will self-bias
to the voltage applied to the VOCM pin.
–INA, –INB (Pins 14, 13): Negative Inputs. These pins are
normally tied together. These inputs may be DC- or AC-
coupled. If the inputs are AC-coupled, they will self-bias
to the voltage applied to the VOCM pin.
Exposed Pad (Pin 17): Tie the pad to VEEC (Pin 12). If split
supplies are used, DO NOT tie the pad to ground.
PI FU CTIO S
UU
U
+
–
14
–INA
5
+OUT
6402 BD
3
VCCA
10
VCCB
1
VCCC
11
ENABLE
13
–INB
14pF
VCCA
A
VEEA
50
6
+OUTFILTERED
–
+
16
+INA
8
–OUT
15
+INB
VCCB
B
VEEB
100
100
100
100
500
500
500
500
50
14pF
7
–OUTFILTERED
12
VEEC
9
VEEB
4
VEEA
+
–
VEEC
C
VCCC
2
VOCM
BIAS
BLOCK DIAGRA
W
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