參數(shù)資料
型號: LT4356CS-3
廠商: LINEAR TECHNOLOGY CORP
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PDSO16
封裝: PLASTIC, SOP-16
文件頁數(shù): 7/24頁
文件大?。?/td> 231K
代理商: LT4356CS-3
LT4356-3
15
43563fa
APPLICATIONS INFORMATION
Shutdown
The LT4356-3 can be shut down to a low current mode
when the voltage at the SHDN pin goes below the shutdown
threshold of 0.6V. The quiescent current drops to 7μA. All
functions are turned off including the auxiliary amplier.
After the GATE pin pulls low due to a fault time out, the
LT4356-3 latches off. Allow sufcient time for the TMR pin
to discharge to 0.5V (typical discharge current is 2.2μA)
and for the MOSFET to cool before attempting to reset the
part. To reset, pull the SHDN pin low for at least 100μs,
then pull high with a slew rate of at least 10V/ms.
The SHDN pin can be pulled up to VCC or below GND by
up to 60V without damaging the pin. Leaving the pin open
allows an internal current source to pull it up and turn
on the part while clamping the pin to 2.5V. The leakage
current at the pin should be limited to no more than 1μA
if no pull up device is used to help turn it on.
Supply Transient Protection
The LT4356-3 is 100% tested and guaranteed to be safe
from damage with supply voltages up to 80V. Nevertheless,
voltage transients above 100V may cause permanent dam-
age. During a short-circuit condition, the large change in
current owing through power supply traces and associated
wiring can cause inductive voltage transients which could
exceed 100V. To minimize the voltage transients, the power
trace parasitic inductance should be minimized by using
wide traces. A small surge suppressor, D2, in Figure 9,
at the input will clamp the voltage spikes.
A total bulk capacitance of at least 22μF low ESR is required
close to the source pin of MOSFET Q1. In addition, the
bulk capacitance should be at least 10 times larger than
the total ceramic bypassing capacitor on the input of the
DC/DC converter.
Layout Considerations
To achieve accurate current sensing, Kelvin connection
to the current sense resistor (RSNS in Figure 9) is recom-
mended. The minimum trace width for 1oz copper foil is
0.02" per amp to ensure the trace stays at a reasonable
temperature. 0.03" per amp or wider is recommended.
Note that 1oz copper exhibits a sheet resistance of about
530μΩ/square. Small resistances can cause large errors in
high current applications. Noise immunity will be improved
signicantly by locating resistive dividers close to the pins
with short VCC and GND traces.
Design Example
As a design example, take an application with the follow-
ing specications: VCC = 8V to 14V DC with transient up
to 80V, VOUT ≤ 16V, current limit (ILIM) at 5A, low battery
detection at 6V, and 1ms of overvoltage early warning
(Figure 9).
Figure 8. Overvoltage Regulator with P-Channel MOSFET
Reverse Input Protection
CTMR
0.1μF
RSNS
10mΩ
Q1
IRLR2908
Q2
Si4435
VIN
12V
VOUT
12V, 3A
CLAMPED AT 16V
43563 F08
LT4356DE-3
GND
TMR
10
1
OUT
SNS
3
5
SHDN
7
AOUT
11
IN+
12
VCC
6
EN
FLT
FB
9
8
2
R2
4.99k
R1
59k
GATE
4
R6
10k
D1
1N5245
15V
R3
10Ω
D2*
SMAJ58CA
*DIODES INC.
Figure 9. Overvoltage Regulator with Low-Battery Detection
CTMR
47nF
*SANYO 25CE22GA
R3
10Ω
RSNS
10mΩ
Q1
IRLR2908
D2
SMAJ58A
VIN
43563 F09
LT4356DE-3
GND
TMR
OUT
GATE
SNS
IN+
SHDN
AOUT
FAULT
EN
FLT
UNDERVOLTAGE
FB
CL*
22μF
DC-DC
CONVERTER
GND
SHDN
VCC
R2
4.99k
R4
383k
R5
100k
R1
59k
10
1
3
4
5
7
12
VCC
6
11
2
9
8
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