參數(shù)資料
型號(hào): LT4356CS-3
廠商: LINEAR TECHNOLOGY CORP
元件分類: 模擬信號(hào)調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PDSO16
封裝: PLASTIC, SOP-16
文件頁數(shù): 5/24頁
文件大?。?/td> 231K
代理商: LT4356CS-3
LT4356-3
13
43563fa
APPLICATIONS INFORMATION
MOSFET stress is the result of power dissipated within
the device. For long duration surges of 100ms or more,
stress is increasingly dominated by heat transfer; this is
a matter of device packaging and mounting, and heatsink
thermal mass. This is analyzed by simulation, using the
MOSFET thermal model.
For short duration transients of less than 100ms, MOSFET
survival is increasingly a matter of safe operating area
(SOA), an intrinsic property of the MOSFET. SOA quanti-
es the time required at any given condition of VDS and
ID to raise the junction temperature of the MOSFET to its
rated maximum. MOSFET SOA is expressed in units of
watt-squared-seconds (P2t). This gure is essentially con-
stant for intervals of less than 100ms for any given device
type, and rises to innity under DC operating conditions.
Destruction mechanisms other than bulk die temperature
distort the lines of an accurately drawn SOA graph so that
P2t is not the same for all combinations of ID and VDS.
In particular P2t tends to degrade as VDS approaches the
maximum rating, rendering some devices useless for
absorbing energy above a certain voltage.
Calculating Transient Stress
To select a MOSFET suitable for any given application, the
SOA stress must be calculated for each input transient
which shall not interrupt operation. It is then a simple matter
to chose a device which has adequate SOA to survive the
maximum calculated stress. P2t for a prototypical transient
waveform is calculated as follows (Figure 4).
Let
a = VREG – VIN
b = VPK – VIN
(VIN = Nominal Input Voltage)
Then
P
2t =I
LOAD
2
1
3
tr
(b a)3
b
+
1
2
2a
2 ln b
a
+ 3a
2 +b2 4ab
Typically VREG ≈ VIN and τ >> tr simplifying the above to
P
2 t =
1
2
ILOAD
2 (V
PK –VREG)
2
(W
2s)
For the transient conditions of VPK = 80V, VIN = 12V, VREG
= 16V, tr = 10μs and τ = 1ms, and a load current of 3A, P2t
is 18.4W2s—easily handled by a MOSFET in a D-pak pack-
age. The P2t of other transient waveshapes is evaluated by
integrating the square of MOSFET power versus time.
Calculating Short-Circuit Stress
SOA stress must also be calculated for short-circuit condi-
tions. Short-circuit P2t is given by:
P2t = (VIN ΔVSNS/RSNS)2 tTMR
(W2s)
where, ΔVSNS is the SENSE pin threshold, and tTMR is the
overcurrent timer interval.
For VIN = 14.7V, VSNS = 50mV, RSNS = 12mΩ and CTMR
= 100nF, P2t is 6.6W2s—less than the transient SOA
calculated in the previous example. Nevertheless, to
account for circuit tolerances this gure should be doubled
to 13.2W2s.
Limiting Inrush Current and GATE Pin Compensation
The LT4356-3 limits the inrush current to any load capaci-
tance by controlling the GATE pin voltage slew rate. An
external capacitor can be connected from GATE to ground
to slow down the inrush current further at the expense of
slower turn-off time. The gate capacitor is set at:
C1 =
I
GATE(UP)
INRUSH
CL
Figure 4. Safe Operating Area Required to Survive Prototypical
Transient Waveform
VPK
VIN
43563 F04
VREG
tr
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