參數(shù)資料
型號: LT4256-3
廠商: Linear Technology Corporation
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Positive High Voltage Hot Swap Controller with Open-Circuit Detect
中文描述: 正高電壓熱插拔控制器與開路檢測
文件頁數(shù): 13/20頁
文件大?。?/td> 305K
代理商: LT4256-3
LT4256-3
13
42563f
APPLICATIU
TIMER
TIMER provides a method for programming the maximum
time the part is allowed to operate in current limit. When
the current limit circuitry is not active, TIMER is pulled to
GND by a 3
μ
A current source. When the current limit
circuitry becomes active, a 118
μ
A pull-up current source
is connected to TIMER and the voltage will rise with a slope
equal to 115
μ
A/C
TIMER
as long as the circuitry stays active.
Once the desired maximum current limit time is known,
the capacitor value is:
W
U
U
C nF
=
25 t ms ; C=115 A
4.65V
μ
t
(6)
Whenever TIMER reaches 4.65V (typ), the internal fault
latch is set causing GATE to be pulled low and TIMER to be
discharged to GND by the 3
μ
A current source. The part is
not allowed to turn on again until the voltage on TIMER
falls below 0.65V (typ).
Whenever GATE is commanded off by any fault condition,
it is discharged with a high current, turning off the external
MOSFET. The waveform in Figure 10 shows how the
output latches off following a current fault. The drop
across the sense resistor is held at 55mV as the timer
ramps up. Once TIMER reaches its shutdown threshold
(4.65V typically), the circuit latches off.
Automatic Restart
If RETRY is floating, then the device automatically restarts
after a current overload fault.
When the voltage at TIMER ramps back down to 0.65V
(typ), the LT4256-3 turns on again. If the short-circuit
condition at the output still exists, the cycle will repeat
itself indefinitely. The duty cycle under short-circuit con-
ditions is 3% which prevents Q1 from overheating. Fig-
ure11 shows representative waveforms during a short
circuit.
Latch Off Operation
If RETRY is grounded, the LT4256-3 will latch off after a
current fault. After the part latches off, it may be com-
manded to start back up. This is accomplished by cycling
UV to ground and then back high (this command can only
be accepted after TIMER discharges below the 0.65V typ
threshold, which prevents overheating transistor Q1).
Figure 10. Latch Off Waveforms
Figure 11. RETRY Waveforms
10ms/DIV
4256 F10
I
500mA/DIV
V
50V/DIV
TIMER
5V/DIV
GATE
50V/DIV
I
500mA/DIV
V
50V/DIV
TIMER
5V/DIV
GATE
50V/DIV
10ms/DIV
4256 F11
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