參數(shù)資料
型號(hào)： LT4180MPGN#TRPBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： 電源管理
英文描述： POWER SUPPLY SUPPORT CKT, PDSO24
封裝： 0.150 INCH, LEAD FREE, PLASTIC, SSOP-24
文件頁(yè)數(shù)： 2/18頁(yè)
文件大?。?/td> 278K
代理商： LT4180MPGN#TRPBF
LT4180
10
4180fa
APPLICATIONS INFORMATION
CLOAD =
2.2
RWIRE 2 fDITHER
Where CLOAD istheminimumloaddecouplingcapacitance,
RWIRE is the minimum wiring resistance of one conduc-
tor of the wiring pair, and fDITHER is the minimum dither
frequency.
Continuing the example, our CAT5 cable has a maximum
9.38Ω/100m conductor resistance.
Maximum wiring resistance is:
RWIRE = 2 1000ft 0.305m/ft 0.0938Ω/m
RWIRE = 57.2Ω
With an oscillator tolerance of ±15%, the minimum
dither frequency is 414.8Hz, so the minimum decoupling
capacitance is:
CLOAD =
2.2
57.2
Ω 2 414.8Hz
= 46.36μF
This is the minimum value. Select a nominal value to ac-
count for all factors which could reduce the nominal, such
as initial tolerance, voltage and temperature coefcients
and aging.
CHOLD Capacitor Selection and Compensation
CHOLD1
A 47nF capacitor will sufce for most applications. A
smaller value might allow faster recovery from a sudden
load change, but care must be taken to ensure full load
p-p ripple at this node is kept within 5mV:
CHOLD2
= CHOLD3 =
2.5nF
fDITHER(kHz)
For a dither frequency of 488Hz:
CHOLD2
= CHOLD3 =
2.5nF
0.488(kHz)
= 5.12nF
NPO ceramic or other capacitors with low leakage and di-
electric absorption should be used for all HOLD capacitors.
Set CHOLD4 to 1μF. This value will be adjusted later.
Compensation
Start with a 47pF capacitor between the COMP and DRAIN
pins of the LT4180. Add an RC network in parallel with the
47pF capacitor, 10k and 10nF are good starting values.
Once the output voltage has been conrmed to regulate
at the desired level at no load, increase the load current
to the100% level and monitor the wire current (Dither
Current) with a current probe. Verify the Dither Current
resembles a square-wave with the desired dither frequency.
If the output voltage is too low, increase the value of the
10k resistor until some overshoot is observed at the leading
edge of the dither current waveform. If the output voltage
is still too low, decrease the value of the 10nF capacitor
and repeat the previous step. Repeat this process until the
full load output voltage increases to within 1% below the
no load level. Refer to Figures 7a, 7b and 7c, which show
compensation of the 12V 1.5A Buck Regulator Application
on the datasheet. Check for proper voltage drop correction
over the load range. The “Dither Current” should have
good half-wave symmetry. Namely, waveform should have
similar rise and fall times, enough settling time at top and
bottom and minimum to no over/undershoot.
20μs/DIV
VLOAD
11.2V
IDITHER
50mA/DIV
4180 F07a
Figure 7a. Dither Current and VOUT with
10nF, 10k Compensation 1.5A Load
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