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參數(shù)資料
| 型號： | LT3581IMSE#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING REGULATOR, PDSO16 |
| 封裝： | LEAD FREE, PLASTIC, MSOP-16 |
| 文件頁數(shù)： | 18/36頁 |
| 文件大小： | 498K |
| 代理商： | LT3581IMSE#PBF |
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LT3581
3581f
appenDix
The use of the external PMOS, controlled by the GATE pin,
is particularly beneficial when dealing with unintended
output shorts in a boost regulator. In a conventional boost
regulator,theinductor,Schottkydiode,andpowerswitches
are susceptible to damage in the event of an output short
toground.UsinganexternalPMOSintheboostregulator’s
power path (path from VINtoVOUT)controlledbytheGATE
pin, will serve to disconnect the input from the output
when the output has a short to ground, thereby helping
save the IC, and the other components in the power path
from damage. Ensure that both, the diode and the inductor
can survive low duty cycle current pulses of 3 to 4 times
their steady state levels.
The PMOS chosen must be capable of handling the maxi-
mum input or output current depending on whether the
PMOS is used at the input (see Figure 11) or the output
(see Figure 18).
Ensure that the PMOS is biased with enough source to
gate voltage (VSG) to enhance the device into the triode
mode of operation. The higher the VSG voltage that biases
the PMOS into triode, the lower the RDSON of the PMOS,
thereby lowering power dissipation in the device during
normal operation, as well as improving the efficiency of
the application in which the PMOS is used. The follow-
ing equations show the relationship between RGATE (see
Block Diagram) and the desired VSG that the PMOS is
biased with:
V
R
k
if V
V
A R
i
SG
IN
GATE
=
+
<
2
933
ff V
V
GATE ≥
2
WhenusingaPMOS,itisadvisabletoconfigurethespecific
application for undervoltage lockout (see the Operations
section). The goal is to have VIN get to a certain minimum
voltage where the PMOS has sufficient headroom to attain
a high enough VSG, which prevents it from entering the
saturation mode of operation during start-up.
Figure 18 shows the PMOS connected in series with the
output to act as an output disconnect during a fault con-
dition. The Schottky diode from the VIN pin to the GATE
pin is optional and helps turn off the PMOS quicker in the
event of hard shorts. The resistor divider from VIN to the
SHDN pin sets a UVLO of 4V for this application.
ConnectingthePMOSinserieswiththeoutputofferscertain
advantages over connecting it in series with the input:
Since the load current is always less than the input
current for a boost converter, the current rating of the
PMOS goes down.
A PMOS in series with the output can be biased with
a higher overdrive voltage than a PMOS used in series
with the input, since VOUT > VIN. This higher overdrive
results in a lower RDSON rating for the PMOS, thereby
improving the efficiency of the regulator.
In contrast, an input connected PMOS works as a simple
hot-plug controller (covered in more detail in the Hot-Plug
section). The input connected PMOS also functions as an
inexpensive means of protecting against multiple output
shorts in boost applications that synchronize the LT3581
with other compatible ICs (see Figure 11).
Table 7 shows a list of several discrete PMOS manufa-
cturers.Consultthemanufacturersfordetailedinformation
on their entire selection of PMOS devices.
Table 7. Discrete PMOS Manufacturers
Vishay
www.vishay.com
Fairchild Semiconductor
www.fairchildsemi.com
COMPENSATION – ADJUSTMENT
To compensate the feedback loop of the LT3581, a series
resistor-capacitor network in parallel with an optional
single capacitor should be connected from the VC pin to
GND. For most applications, choose a series capacitor in
the range of 1nF to 10nF with 2.2nF being a good starting
value. The optional parallel capacitor should range in value
from 47pF to 160pF with 100pF being a good starting
value. The compensation resistor, RC, is usually in the
range of 5k to 50k with 10k being a good starting value.
A good technique to compensate a new application is to
use a 100k potentiometer in place of the series resistor RC.
With the series and parallel capacitors at 2.2nF and 100pF
respectively, adjust the potentiometer while observing the
transient response and the optimum value for RC can be
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| LT3582EUD#PBF | 功能描述:IC REG BOOST INV ADJ DL 16QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 開關(guān)穩(wěn)壓器 系列:- 標準包裝:250 系列:- 類型:降壓（降壓） 輸出類型:固定 輸出數(shù):1 輸出電壓:1.2V 輸入電壓:2.05 V ~ 6 V PWM 型:電壓模式 頻率 - 開關(guān):2MHz 電流 - 輸出:500mA 同步整流器:是 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:6-UFDFN 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:6-SON（1.45x1） 產(chǎn)品目錄頁面:1032 (CN2011-ZH PDF) 其它名稱:296-25628-2 |
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