參數(shù)資料
型號(hào)： LT3581IDE#TRPBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： 穩(wěn)壓器
英文描述： SWITCHING REGULATOR, PDSO14
封裝： 4 X 3 MM, 0.75 MM HEIGHT, LEAD FREE, PLASTIC, MO-229WGED-3, DFN-14
文件頁數(shù)： 8/36頁
文件大小： 498K
代理商： LT3581IDE#TRPBF
LT3581
3581f
3581 F08
VOUT
CIN
B
A
SYNC
GND
A: RETURN CIN GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED TO NOT
COMBINE CIN GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
B: RETURN COUT AND COUT1 GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED
TO NOT COMBINE COUT AND COUT1 GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
SHDN
CLKOUT
+
–
VIN
+
–
L1
17
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
COUT1
RGATE
COUT
D1
M1
D2
applicaTions inForMaTion
LAYOUT GUIDELINES FOR BOOST, SEPIC, AND DUAL
INDUCTOR INVERTING TOPOLOGIES
General Layout Guidelines
To optimize thermal performance, solder the exposed
ground pad of the LT3581 to the ground plane, with
multiple vias around the pad connecting to additional
ground planes.
Agroundplaneshouldbeusedundertheswitchercircuitry
to prevent interplane coupling and overall noise.
High speed switching path (see specific topology for
more information) must be kept as short as possible.
The VC, FB, and RT components should be placed as
close to the LT3581 as possible, while being as far
away as practically possible from the switch node. The
groundforthesecomponentsshouldbeseparatedfrom
the switch current path.
Place the bypass capacitor for the VIN pin as close as
possible to the LT3581.
Place the bypass capacitor for the inductor as close as
possible to the inductor.
The load should connect directly to the positive and
negative terminals of the output capacitor for best load
regulation.
Boost Topology Specific Layout Guidelines
Keep length of loop (high speed switching path) gov-
erning switch, diode D1, output capacitor COUT1, and
ground return as short as possible to minimize parasitic
inductive spikes at the switch node during switching.
SEPIC Topology Specific Layout Guidelines
Keep length of loop (high speed switching path) gov-
erning switch, flying capacitor C1, diode D1, output
capacitor COUT, and ground return as short as possible
tominimizeparasiticinductivespikesattheswitchnode
during switching.
Inverting Topology Specific Layout Guidelines
Keep ground return path from the cathode of D1 (to
chip) separated from output capacitor COUT’s ground
return path (to chip) in order to minimize switching
noise coupling into the output.
Keeplengthofloop(highspeedswitchingpath)govern-
ing switch, flying capacitor C1, diode D1, and ground
return as short as possible to minimize parasitic induc-
tive spikes at the switch node during switching.
Figure 8. Suggested Component Placement for Boost Topology
(MSOP Shown, DFN Similar, Not to Scale.) Pin 15 on DFN or
Pin 17 on MSOP Is the Exposed Pad Which Must Be Soldered
Directly to the Local Ground Plane for Adequate Thermal
Performance. Multiple Vias to Additional Ground Planes Will
Improve Thermal Performance
Figure 9. Suggested Component Placement for SEPIC Topology
(MSOP Shown, DFN Similar, Not to Scale.) Pin 15 on DFN or
Pin 17 on MSOP Is the Exposed Pad Which Must Be Soldered
Directly to the Local Ground Plane for Adequate Thermal
Performance. Multiple Vias to Additional Ground Planes Will
Improve Thermal Performance
3581 F09
VOUT
CIN
C1
D1
B
A
SYNC
GND
A: RETURN CIN AND L2 GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED
TO NOT COMBINE CIN AND L2 GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
B: RETURN COUT GROUNDS DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED
TO NOT COMBINE COUT GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
L1, L2: MOST COUPLED INDUCTOR MANUFACTURERS USE CROSS PINOUT FOR IMPROVED
PERFORMANCE.
COUT
SHDN
CLKOUT
+
–
VIN
+
–
L2
L1
17
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
相關(guān)PDF資料
PDF描述
LT3581IMSE#TRPBF SWITCHING REGULATOR, PDSO16
LT3581IMSE#PBF SWITCHING REGULATOR, PDSO16
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LT3682EDD#TRPBF SWITCHING REGULATOR, PDSO12
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