參數(shù)資料
型號(hào)： LT3507HUHF#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 9/28頁(yè)
文件大?。?/td> 302K
描述： IC REG QD BUCK/LINEAR 38-QFN
產(chǎn)品培訓(xùn)模塊： More Information on LDOs
標(biāo)準(zhǔn)包裝： 2,500
拓?fù)洌?/td> 降壓（降壓）（1），線性（LDO）（1）
功能： 任何功能
輸出數(shù)： 4
頻率 - 開關(guān)： 900kHz ~ 1.1MHz
電壓/電流 - 輸出 1： 0.8 V ~ 32.4 V，2.4A
電壓/電流 - 輸出 2： 0.8 V ~ 32.4 V，1.5A
電壓/電流 - 輸出 3： 0.8 V ~ 32.4 V，1.5A
帶 LED 驅(qū)動(dòng)器： 無(wú)
帶監(jiān)控器： 無(wú)
帶序列發(fā)生器： 是
電源電壓： 4 V ~ 36 V
工作溫度： -40°C ~ 150°C
安裝類型： 表面貼裝
封裝/外殼： 38-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 38-QFN（5x7）
包裝： 帶卷 (TR)
LT3507
9
3507fa
OPERATION
The LT3507 contains three independent, constant fre-
quency, current mode, switching regulators with internal
power switches plus a low dropout linear regulator. The
three regulators share common circuitry including input
source, voltage reference and oscillator, but are otherwise
independent. Operation can be best understood by refer-
ring to the Block Diagram (Figure 1).
If the RUN pins are tied to ground, the LT3507 is shut
down and draws <1糀 from the input source tied to V
IN1
.
If any of the RUN pins are driven above 1V, the internal bias
circuits turn on, including the internal regulator, reference,
and master oscillator. Each switching regulator will only
begin to operate when its corresponding RUN pin reaches
>1.25V. The master oscillator generates three clock signals,
with the signal for Channel 1 out of phase by 180?
The three switchers are current mode regulators. Instead
of directly modulating the duty cycle of the power switch,
the feedback loop controls the peak current in the switch
during each cycle. Compared to voltage mode control, cur-
rent mode control improves loop dynamics and provides
cycle-by-cycle current limit.
The Block Diagram shows only one of the three step-down
switching regulators. A pulse from the slave oscillator
sets the RS  ip- op and turns on the internal NPN bipo-
lar power switch. Current in the switch and the external
inductor begins to increase. When this current exceeds a
level determined by the voltage at V
C
, current comparator
C1 resets the  ip- op, turning off the switch. The current
in the inductor  ows through the external Schottky diode
and begins to decrease. The cycle begins again at the next
pulse from the oscillator. In this way, the voltage on the
V
C
 pin controls the current through the inductor to the
output. The internal error ampli er regulates the output
voltage by continually adjusting the V
C
 pin voltage. The
threshold for switching on the V
C
 pin is >1V and an active
clamp of 1.8V limits the output current.
Each switcher contains an extra, independent oscillator to
perform frequency foldback during overload conditions.
This slave oscillator is normally synchronized to the master
oscillator. A comparator senses when V
FB
 is less than 50%
of its regulated value and switches the regulator from the
master oscillator to a slower slave oscillator. V
FB
 is less than
50% of its regulated value during start-up, short-circuit
and overload conditions. Frequency foldback helps limit
switch current under these conditions.
The TRK/SS pins override the 0.8V reference for the FB
pins when the TRK/SS pins are below 0.8V. This allows
either coincident or ratiometric supply tracking on start-up
as well as a soft-start capability.
The switch drivers operate either from V
IN
 or from the
BOOST pin. An external capacitor and diode are used to
generate a voltage at the BOOST pin that is higher than the
input supply. This allows the driver to saturate the internal
bipolar NPN power switch for ef cient operation.
The BIAS pin allows the internal circuitry to draw its current
from a lower voltage supply than the input, also reducing
power dissipation and increasing ef ciency. If the voltage
on the BIAS pin falls below 3V, then its quiescent current
will  ow from V
IN
.
A power good comparator trips when the FB pin is at
90% of its regulated value. The PGOOD output is an
open-collector transistor that is off when the output is in
regulation, allowing an external resistor to pull the PGOOD
pin high. Power good is valid when the LT3507 is enabled
and V
IN
 > 3.5V.
The LDO regulator uses an external NPN pass transistor to
form a linear regulator. The loop is internally compensated
to be stable with a load capacitance of 2.2糉 or greater.
The LDO is disabled when all three of the RUN pins are
low.
The overvoltage and undervoltage detection shuts down
the LT3507 if the input voltage goes above or below re-
sistor programmable thresholds. The hysteresis of these
detectors is also resistor programmable.
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