參數(shù)資料
型號: LT3507HUHF#TRPBF
廠商: Linear Technology
文件頁數(shù): 19/28頁
文件大?。?/td> 302K
描述: IC REG QD BUCK/LINEAR 38-QFN
產(chǎn)品培訓模塊: More Information on LDOs
標準包裝: 2,500
拓撲: 降壓(降壓)(1),線性(LDO)(1)
功能: 任何功能
輸出數(shù): 4
頻率 - 開關: 900kHz ~ 1.1MHz
電壓/電流 - 輸出 1: 0.8 V ~ 32.4 V,2.4A
電壓/電流 - 輸出 2: 0.8 V ~ 32.4 V,1.5A
電壓/電流 - 輸出 3: 0.8 V ~ 32.4 V,1.5A
帶 LED 驅動器:
帶監(jiān)控器:
帶序列發(fā)生器:
電源電壓: 4 V ~ 36 V
工作溫度: -40°C ~ 150°C
安裝類型: 表面貼裝
封裝/外殼: 38-WFQFN 裸露焊盤
供應商設備封裝: 38-QFN(5x7)
包裝: 帶卷 (TR)
LT3507
19
3507fa
the TRK/SS2 voltage is substantially higher than 0.8V at
steady state and effectively turns off D1. D2 and D3 will
therefore conduct the same current and offer tight matching
between V
FB2
 and the internal precision 0.8V reference. In
the ratiometric mode with R6 = R2, TRK/SS2 equals 0.8V
at steady state. D1 will divert part of the bias current and
make V
FB2
 slightly lower than 0.8V. Although this error
is minimized by the exponential I-V characteristic of the
diodes, it does impose a  nite amount of output voltage
deviation. Further, when channel 1s output experiences
dynamic excursions (under load transient, for example),
channel 2 will be affected as well. Setting R6 to a value
that pushes the TRK/SS2 voltage to 1V at steady state will
eliminate these problems while providing near ratiometric
tracking.
The example shows channel 2 tracking channel 1, however
any channel may be set up to track any other channel.
If a capacitor is tied from the TRK/SS pin to ground, then
the internal pull-up current will generate a voltage ramp on
this pin. This results in a ramp at the output, limiting the
inductor current and therefore input current during start-up.
A good value for the soft-start capacitor is C
OUT
/10,000,
where C
OUT
 is the value of the output capacitor.
MULTIPLE INPUT SUPPLIES
V
IN1
, V
IN2
 and V
IN3
 are independent and can be powered
with different voltages provided V
IN1
 is present when V
IN2
 
or V
IN3
 is present. Each supply must be bypassed as close
to the V
IN
 pins as possible.
For applications requiring large inductors due to high V
IN
 
to V
OUT
 ratios, a 2-stage step-down approach may reduce
inductor size by allowing an increase in frequency. A dual
step-down application steps down the input voltage (V
IN1
)
to the highest output voltage, then uses that voltage to
power the other outputs (V
IN2
 and V
IN3
). V
OUT1
 must be
able to provide enough current for its output plus the
input current at V
IN2
 and V
IN3
 when V
OUT2
 and V
OUT3
 are
at maximum load. The Typical Applications section shows
a 36V to 15V, 1.8V and 1.2V 2-stage converter using this
approach.
For applications with multiple voltages, the LT3507 can
accommodate input voltages as low as 3V on V
IN2
 and
APPLICATIONS INFORMATION
V
IN3
. This can be useful in applications regulating outputs
from a PCI Express bus, where the 12V input is power
limited and the 3.3V input has power available to drive
other outputs. In this case, tie the 12V input to V
IN1
 and
the 3.3V input to V
IN2
 and V
IN3
.
LOW DROPOUT REGULATOR
The low dropout regulator comprises an error amp, loop
compensation and a base drive amp. It uses the same
0.8V reference as the switching regulators. It requires an
external NPN pass transistor and 2.2糉 of output capaci-
tance for stability.
The dropout characteristics will be determined by the pass
transistor. The collector-emitter saturation characteristics
will limit the dropout voltage. Table 4 lists some suitable
NPN transistors with their saturation speci cations.
The base drive voltage has a maximum voltage of 5V.
This will limit the maximum output of the regulator to
5V  V
BESAT
 where V
BESAT
 is the base-emitter saturation
voltage of the pass transistor.
Table 4. NPN Pass Transistors and Saturation Characteristics
PART NUMBER
V
CESAT
V
BESAT
I
C
 (mA)  I
B
 (mA)
On Semiconductor
NSS30071
0.25    0.85    500
5
NSS30101
0.2    0.85    1000    10
Fairchild
KSC3265
0.4
500    20
The LDO is always on when any of the switcher channels
is on. The LDO may be shut down if it is unused by pull-
ing the FB4 pin up with a 30糀 current source. The FB4
pin will clamp at about 1.25V and the LDO will shut off
reducing power consumption. This pull-up can be sourced
from one of the LT3507 outputs provided that channel is
always on when the other channels are on.
The output stage of the LDO will drive the NPN base from
the BIAS voltage if it is at least 0.8V above the LDO DRIVE
voltage.
FB Resistor Network
The output voltage of the LDO regulator is programmed
with a resistor divider (Refer to Block Diagram) between the
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