參數(shù)資料
型號: LT3437
廠商: Linear Technology Corporation
英文描述: Panels; For Use With:EUROCARD Subracks RoHS Compliant: Yes
中文描述: 高電壓,200kHz降壓500mA的降壓開關穩(wěn)壓器以100?的靜態(tài)電流
文件頁數(shù): 18/24頁
文件大小: 523K
代理商: LT3437
LT3437
18
3437f
APPLICATIOU
inductance of approximately 25nH/inch. At switch off, this
parasitic inductance produces a flyback spike across the
LT3437 switch. When operating at higher currents and
input voltages, with poor layout, this spike can generate
voltages across the LT3437 that may exceed its absolute
maximum rating. A ground plane should always be used
under the switcher circuitry to prevent interplane coupling
and overall noise.
W
U
U
The V
C
and FB components should be kept as far away as
possible from the switch and boost nodes. The LT3437
pinout has been designed to aid in this. The ground for
these components should be separated from the switch
current path. Failure to do so will result in poor stability or
subharmonic oscillation.
Board layout also has a significant effect on thermal
resistance. Pin 4/Pin 10 and the exposed die pad, Pin 11/
Pin 17, are connected by a continuous copper plate that
runs under the LT3437 die. This is the best thermal path
for heat out of the package. Reducing the thermal resis-
tance from Pin 4 and the exposed pad onto the board will
reduce die temperature and increase the power capability
of the LT3437. This is achieved by providing as much
copper area as possible around the exposed pad. Adding
multiple solder filled feedthroughs, under and around this
pad, to an internal ground plane will also help. Similar
treatment to the catch diode and coil terminations will
reduce any additional heating effects.
THERMAL CALCULATIONS
Power dissipation in the LT3437 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current, and input quiescent current. The following formu-
las show how to calculate each of these losses. These
formulas assume continuous mode operation, and should
not be used for calculating efficiency at light load currents.
Switch loss:
P
R
V
V
t
I
V
f
SW
SW OUT
OUT
IN
EFF
OUT
IN
=
) (
)
+
(
)(
)( )( )
2
1 2
Boost current loss:
P
V
I
V
BOOST
OUT
OUT
IN
=
(
)
(
)
2
30
/
Quiescent current loss:
P
Q
= V
IN
(500
μ
A) + V
OUT
(800
μ
A)
R
SW
= switch resistance (
1 when hot )
t
EFF
= effective switch current/voltage overlap time
Figure 9. Suggested Layouts
Figure 8. High Speed Switching Path
C2
C1
3437 F08
D1
L1
V
IN
LT3437
V
OUT
V
IN
SW
HIGH
FREQUENCY
CIRCULATION
PATH
+
LOAD
3437 F09b
DD PACKAGE TOPSIDE METAL
C1
C2
D1
L1
3437 F09a
FE PACKAGE TOPSIDE METAL
D1
C1
C2
L1
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