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參數(shù)資料
| 型號(hào)： | LT1993IUD-4#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DIFF AMP/ADC DRVR 16-QFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 放大器類型： | 差分 |
| 電路數(shù)： | 2 |
| 輸出類型： | 差分 |
| 轉(zhuǎn)換速率： | 1100 V/µs |
| -3db帶寬： | 900MHz |
| 電流 - 輸入偏壓： | 5µA |
| 電壓 - 輸入偏移： | 1000µV |
| 電流 - 電源： | 100mA |
| 電流 - 輸出 / 通道： | 45mA |
| 電壓 - 電源，單路/雙路(±)： | 4 V ~ 5.5 V，±2 V ~ 2.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 16-QFN-EP（3x3） |
| 包裝： | 帶卷 (TR) |
LT1993-4
10
19934fa
+OUTFILTERED, –OUTFILTERED (Pins 6, 7): Filtered
Outputs. These pins add a series 25
Ω resistor from the
unltered outputs and three 12pF capacitors. Each output
has 12pF to VEE, plus an additional 12pF between each pin
(See the Block Diagram). This lter has a –3dB bandwidth
of 175MHz.
ENABLE (Pin 11): This pin is a TTL logic input referenced
to the VEEC pin. If low, the LT1993-4 is enabled and draws
typically 100mA of supply current. If high, the LT1993-4
is disabled and draws typically 250A.
–INA, –INB (Pins 14, 13): Negative Inputs. These pins are
normally tied together. These inputs may be DC- or AC-
coupled. If the inputs are AC-coupled, they will self-bias
to the voltage applied to the VOCM pin.
+INA, +INB (Pins 16, 15): Positive Inputs. These pins are
normally tied together. These inputs may be DC- or AC-
coupled. If the inputs are AC-coupled, they will self-bias
to the voltage applied to the VOCM pin.
Exposed Pad (Pin 17): Tie the pad to VEEC (Pin 12). If split
supplies are used, DO NOT tie the pad to ground.
PI FU CTIO S
UU
U
+
–
14
–INA
5
+OUT
19934 BD
3
VCCA
10
VCCB
1
VCCC
11
ENABLE
13
–INB
12pF
VCCA
A
VEEA
100
100
200
200
25
200
6
+OUTFILTERED
–
+
16
+INA
8
–OUT
15
+INB
VCCB
B
VEEB
100
100
25
200
12pF
7
–OUTFILTERED
12
VEEC
9
VEEB
4
VEEA
+
–
VEEC
C
VCCC
2
VOCM
BIAS
BLOCK DIAGRA
W
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