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參數(shù)資料
| 型號： | LT1977 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | High Voltage 1.5A, 500kHz Step-Down Switching Regulator with 100uA Quiescent Current |
| 中文描述： | 高電壓，500kHz降壓1.5安培的電流型開關穩(wěn)壓器的靜態(tài)電流為100uA |
| 文件頁數(shù)： | 15/24頁 |
| 文件大小： | 288K |
| 代理商： | LT1977 |
LT1977
15
1977f
APPLICATIOU
low value such that the current doesn’t continue to ratchet
higher. When the FB pin voltage is abnormally low thereby
indicating some sort of short-circuit condition, the oscil-
lator frequency will be reduced. Oscillator frequency is
reduced by a factor of 4 when the FB pin voltage is below
0.4V and increases linearly to its typical value of 500kHz at
a FB voltage of 0.95V (see Typical Performance Character-
istics). In addition, if the current in the switch exceeds 1.5
I
PK
current demanded by the V
C
pin, the LT1977 will skip
the next on cycle effectively reducing the oscillator fre-
quency by a factor of 2. These oscillator frequency reduc-
tions during short-circuit conditions allow the LT1977 to
maintain current control.
W
U
U
SOFT-START
For applications where [V
IN
/(V
OUT
+ V
F
)] ratios > 10 or
large input surge currents can’t be tolerated, the LT1977
soft-start feature should be used to control the output
capacitor charge rate during start-up, or during recovery
from an output short circuit thereby adding additional
control over peak inductor current. The soft-start function
limits the switch current via the V
C
pin to maintain a
constant voltage ramp rate (dV/dt) at the output capacitor.
A capacitor (C1 in Figure 2) from the C
SS
pin to the
regulated output voltage determines the output voltage
ramp rate. When the current through the C
SS
capacitor
exceeds the C
SS
threshold (I
CSS
), the voltage ramp of the
output capacitor is limited by reducing the V
C
pin voltage.
The C
SS
threshold is proportional to the FB voltage (see
Typical Performance Characteristics) and is defeated for
FB voltages greater than 0.9V (typical). The output dV/dt
can be approximated by:
dV
dt
I
C
CSS
SS
=
but actual values will vary due to start-up load conditions,
compensation values and output capacitor selection.
Burst Mode OPERATION
T
o enhance efficiency at light loads, the LT1977 automati-
cally switches to Burst Mode operation (see Typical
Performance Characteristics) which keeps the output
Figure 4. V
OUT
dV/dt
V
1V/DIV
V
IN
= 12V
V
OUT
= 3.3V
1ms/DIV
1977 F04
C
CSS
= 1000pF
C
CSS
= 0.01
μ
F
C
CSS
= 0.1
μ
F
capacitor charged to the proper voltage while minimizing
the input quiescent current. During Burst Mode opera-
tion, the LT1977 delivers short bursts of current to the
output capacitor followed by sleep periods where the
output power is delivered to the load by the output
capacitor. In addition, V
IN
and BIAS quiescent currents
are reduced to typically 45
μ
A and 125
μ
A respectively
during the sleep time. As the load current decreases
towards a no load condition, the percentage of time that
the LT1977 operates in sleep mode increases and the
average input current is greatly reduced resulting in
higher efficiency.
The minimum average input current depends on the V
IN
to
V
OUT
ratio, V
C
frequency compensation, feedback divider
network and Schottky diode leakage. It can be approxi-
mated by the following equation:
I
I
I
V
V
I
I
I
IN AVG
(
VINS
SHDN
OUT
IN
BIASS
FB
S
)
+
+
+
( )
η
+
(
)
where:
I
VINS
= input pin current in sleep mode
V
OUT
= output voltage
V
IN
=
input voltage
I
BIASS
= BIAS pin current in sleep mode
I
FB
= feedback network current
I
S
= catch diode reverse leakage at V
OUT
η
= low current efficiency (non Burst Mode operation)
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