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參數(shù)資料
| 型號： | LT1969CMS#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 2/20頁 |
| 文件大小： | 0K |
| 描述： | IC OP-AMP ADJ CURRNT DUAL 10MSOP |
| 標準包裝： | 2,500 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 2 |
| 轉(zhuǎn)換速率： | 200 V/µs |
| 增益帶寬積： | 700MHz |
| 電流 - 輸入偏壓： | 1.5µA |
| 電壓 - 輸入偏移： | 1000µV |
| 電流 - 電源： | 7mA |
| 電流 - 輸出 / 通道： | 700mA |
| 電壓 - 電源，單路/雙路(±)： | 4 V ~ 13 V，±2 V ~ 6.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | LT1969CMSTR |
10
LT1969
Input Considerations
The inputs of the LT1969 are an NPN differential pair
protected by back-to-back diodes (see the Simplified
Schematic). There are no series protection resistors
onboard which would degrade the input voltage noise. If
the inputs can have a voltage difference of more than 0.7V,
the input current should be limited to less than 10mA with
external resistance (usually the feedback resistor or source
resistor). Each input also has two ESD clamp diodes—one
to each supply. If an input drive exceeds the supply, limit
the current with an external resistor to less than 10mA.
The LT1969 design is a true operational amplifier with high
impedance inputs and low input bias currents. The input
offset current is a factor of ten lower than the input bias
current. To minimize offsets due to input bias currents,
match the equivalent DC resistance seen by both inputs.
The low input noise current can significantly reduce total
noise compared to a current feedback amplifier, especially
for higher source resistances.
Layout and Passive Components
With a gain bandwidth product of 700MHz the LT1969
requires attention to detail in order to extract maximum
performance. Use a ground plane, short lead lengths and
a combination of RF-quality supply bypass capacitors
(i.e., 470pF and 0.1
F). As the primary applications have
high drive current, use low ESR supply bypass capacitors
(1
F to 10F). For best distortion performance with high
drive current a capacitor with the shortest possible trace
lengths should be placed between Pins 1 and 5. The
optimum location for this capacitor is on the back side of
the PC board.
The parallel combination of the feedback resistor and gain
setting resistor on the inverting input can combine with
the input capacitance to form a pole which can cause
frequency peaking. In general, use feedback resistors of
1k
or less.
Thermal Issues
The LT1969 enhanced
θJA MS10 package has the V– pin
fused to the lead frame. This thermal connection increases
the efficiency of the PC board as a heat sink. The PCB
material can be very effective at transmitting heat between
the pad area attached to the V– pin and a ground or power
plane layer. Copper board stiffeners and plated through-
holes can also be used to spread the heat generated by the
device. Table 1 lists the thermal resistance for several
different board sizes and copper areas. All measurements
Large-Signal Transient, AV = 10,
Low Power**
Large-Signal Transient, AV = – 10,
Low Power**
1969 G41
1969 G42
APPLICATIO S I FOR ATIO
WU
UU
TYPICAL PERFOR A CE CHARACTERISTICS
UW
*13k RESISTOR FROM CTRL1 TO V– AND A 49.9k RESISTOR FROM CTRL2 TO V–
** 49.9k RESISTOR FROM CTRL2 TO V–, CTR1 FLOATING
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