9
LT1395/LT1396/LT1397
Capacitance on the Inverting Input
Current feedback amplifiers require resistive feedback
from the output to the inverting input for stable operation.
Take care to minimize the stray capacitance between the
output and the inverting input. Capacitance on the invert-
ing input to ground will cause peaking in the frequency
response (and overshoot in the transient response).
Capacitive Loads
The LT1395/LT1396/LT1397 can drive many capacitive
loads directly when the proper value of feedback resistor
is used. The required value for the feedback resistor will
increase as load capacitance increases and as closed-loop
gain decreases. Alternatively, a small resistor (5
to 35
)
can be put in series with the output to isolate the capacitive
load from the amplifier output. This has the advantage that
the amplifier bandwidth is only reduced when the capaci-
tive load is present. The disadvantage is that the gain is a
function of the load resistance. See the Typical Perfor-
mance Characteristics curves.
Power Supplies
The
LT1395/LT1396/LT1397
will operate from single or
split supplies from
±
2V (4V total) to
±
6V (12V total). It
is not necessary to use equal value split supplies, how-
ever the offset voltage and inverting input bias current
will change. The offset voltage changes about 2.5mV per
volt of supply mismatch. The inverting bias current will
typically change about 10
μ
A per volt of supply mismatch.
Slew Rate
Unlike a traditional voltage feedback op amp, the slew rate
of a current feedback amplifier is not independent of the
amplifier gain configuration. In a current feedback ampli-
fier, both the input stage and the output stage have slew rate
limitations. In the inverting mode, and for gains of 2 or more
in the noninverting mode, the signal amplitude between the
input pins is small and the overall slew rate is that of the
output stage. For gains less than 2 in the noninverting mode,
the overall slew rate is limited by the input stage.
The input slew rate of the
LT1395/LT1396/LT1397
is
approximately 600V/
μ
s and is set by internal currents and
capacitances. The output slew rate is set by the value of
U
S
A
O
PPLICATI
IU
U
the feedback resistor and internal capacitance. At a gain
of 2 with 255
feedback and gain resistors and
±
5V
supplies, the output slew rate is typically 800V/
μ
s. Larger
feedback resistors will reduce the slew rate as will lower
supply voltages.
Enable/Disable
The LT1395CS6 has a unique high impedance, zero
supply current mode which is controlled by the EN pin.
The LT1395CS6 is designed to operate with CMOS logic;
it draws virtually zero current when the EN pin is high. To
activate the amplifier, its EN pin is normally pulled to a
logic low. However, supply current will vary as the voltage
between the V
+
supply and EN is varied. As seen in Figure
1, +I
S
does vary with (V
+
– V
EN
), particularly when the
voltage difference is less than 3V. For normal operation,
it is important to keep the EN pin at least 3V below the V
+
supply. If a V
+
of less than 3V is desired, and the amplifier
will remain enabled at all times, then the EN pin should be
tied to the V
–
supply. The enable pin current is approxi-
mately 30
μ
A when activated. If using CMOS open-drain
logic, an external 1k pull-up resistor is recommended to
ensure that the LT1395CS6 remains disabled in spite of
any CMOS drain leakage currents.
The enable/disable times are very fast when driven from
standard 5V CMOS logic. The LT1395CS6 enables in
about 30ns (50% point to 50% point) while operating on
±
5V supplies (Figure 2). Likewise, the disable time is
approximately 40ns (50% point to 50% point) (Figure 3).
Figure 1. +I
S
vs (V
+
– V
EN
)
V
+
– V
EN
(V)
0
0
+
S
0.5
1.5
2.0
2.5
5.0
3.5
2
4
5
1395/6/7 F01
1.0
4.0
4.5
3.0
1
3
6
7
T
A
= 25
°
C
V
+
= 5V
V
–
= –5V
V
–
= 0V