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參數(shù)資料
| 型號： | LT1394CS8#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMPARATOR LOW PWR 7NS 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | UltraFast™ |
| 類型： | 帶鎖銷 |
| 元件數(shù)： | 1 |
| 輸出類型： | CMOS，補(bǔ)充型，TTL |
| 電壓 - 輸入偏移（最小值）： | 2.5mV @ ±5V |
| 電流 - 輸入偏壓（最小值）： | 4.5µA @ ±5V |
| 電流 - 輸出（標(biāo)準(zhǔn)）： | 20mA |
| 電流 - 靜態(tài)（最大值）： | 8.5mA |
| CMRR, PSRR（標(biāo)準(zhǔn)）： | 100dB CMRR，100dB PSRR |
| 傳輸延遲（最大）： | 9ns |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 安裝類型： | 表面貼裝 |
| 包裝： | 帶卷 (TR) |
14
LT1394
High Speed Adaptive Trigger Circuit
Line and fibre-optic receivers often require an adaptive
trigger to compensate for variations in signal amplitude
and DC offsets. The circuit in Figure 18 triggers on 2mV to
175mV signals from 100Hz to 45MHz while operating from
a single 5V rail. A1, operating at a gain of 15, provides
wideband AC gain. The output of this stage biases a 2-way
peak detector (Q1 through Q4). The maximum peak is
stored in Q2’s emitter capacitor, while the minimum excur-
sion is retained in Q4’s emitter capacitor. The DC value of
the midpoint of A1’s output signal appears at the junction
of the 500pF capacitor and the 3M
units. This point
always sits midway between the signal’s excursions,
egardless of absolute amplitude. This signal-adaptive volt-
age is buffered by A2 to set the trigger voltage at the
LT1394’s positive input. The LT1394’s negative input is
biased directly from A1’s output. The LT1394’s output, the
circuit’s output, is unaffected by >85:1 signal amplitude
variations. Bandwidth limiting in A1 does not affect trigger-
ing because the adaptive trigger threshold varies
ratiometrically to maintain circuit output.
APPLICATIONS INFORMATION
WU
U
Figure 19 shows operating waveforms at 45MHz. Trace A’s
input produces Trace B’s amplified output at A1. The
comparator’s output is Trace C.
Split supply versions of this circuit can achieve band-
widths to 50MHz with wider input operating range.
A = 0.1V/DIV
B = 0.1V/DIV
C = 5V/DIV
50ns/DIV
AN72 F64
Figure 19. Adaptive Trigger Responding to a 40MHz,
5mV Input. Input Amplitude Variations from 2mV to
175mV Are Accommodated
5V
–
+
A1
LT1227
–
+
A2
LT1006
INPUT
5V
TRIGGER
OUT
1394 F18
500pF
0.1
F
510
470
470
750
36
1
3
2
4
14
13
15
5
6
12
10
11
2k
10
F
2k
+
0.1
F
0.1
F
0.005
F
0.005
F
100
F
+
Q1, Q2, Q3, Q4 = CA3096 ARRAY:
TIE SUBSTRATE (PIN 16) TO GROUND
= 1N4148
–
+
LT1394
Q1
Q2
Q3
Q4
3M
Figure 18. 45MHz Single Supply Adaptive Trigger. Output Comparator’s
Threshold Varies Ratiometrically with Input Amplitude, Maintaining Data
Integrity over > 85:1 Input Amplitude Range
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