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參數(shù)資料
| 型號： | LT1123CST#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 161K |
| 描述： | IC REG CTRLR SGL 5V SOT223 |
| 產(chǎn)品培訓(xùn)模塊： | More Information on LDOs |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 正，固定式 |
| 輸出數(shù)： | 1 |
| 輸出電壓： | 5V |
| 電流 - 電源： | 700µA |
| 工作溫度： | 0°C ~ 125°C |
| 封裝/外殼： | TO-261-4，TO-261AA |
| 供應(yīng)商設(shè)備封裝： | SOT-223 |
| 包裝： | 帶卷 (TR) |
9
LT1123
1123fb
voltage and resistor value. Power dissipation can be
calculated using the following formula:
P
V V V
R
RD
IN BE DRIVE
2
=
(
)
where:
V
BE
= emitter/base voltage of the PNP pass transistor
V
DRIVE
= voltage at the drive pin of the LT1123
= V
SAT
of the drive pin in the worst case
The worst-case power dissipation in the PNP pass transis-
tor is simply equal to:
P
MAX
= (V
IN
V
OUT
)(I
OUT
)
where
V
IN
= Maximum V
IN
I
OUT
= Maximum I
OUT
The thermal resistance of the MJE1123 is equal to:
70癈/W Junction to Ambient (no heat sink)
1.67癈/W Junction to Case
The PNP will normally be attached to either a chassis or a
heat sink so the actual thermal resistance from junction to
ambient will be the sum of the PNPs junction to case
thermal resistance and the thermal resistance of the heat
sink or chassis. For nonstandard heat sinks the user will
need to determine the thermal resistance by experiment.
The maximum junction temperature rise above ambient
for the PNP pass transistor will be equal to the maximum
power dissipation times the thermal resistance, junction
to ambient, of the PNP. The maximum operating junction
temperature of the MJE1123 is 150癈. The maximum
operating ambient temperature for the MJE1123 will be
equal to 150癈 minus the maximum junction temperature
rise.
The SOT-223 package is designed to be surface mounted.
Heat sinking is accomplished by using the heat spreading
capabilities of the PC board and its copper traces. The
thermal resistance from junction to ambient can be as low
as 50癈/W. This requires a reasonably sized PC board with
at least one layer of copper to spread the heat across the
board and couple it into the surrounding air.
The table below can be used as a guideline in estimating
thermal resistance. Data for the table was generated using
1/16" FR-4 board with 1oz copper foil.
Table 1.
Copper Area
Thermal Resistance
Topside*
Backside
Board Area (Junction to Ambient)
2500 sq. mm 2500 sq. mm
2500 sq. mm
50癈/W
1000 sq. mm 2500 sq. mm
2500 sq. mm
50癈/W
225 sq. mm
2500 sq. mm
2500 sq. mm
58癈/W
100 sq. mm
2500 sq. mm
2500 sq. mm
64癈/W
1000 sq. mm 1000 sq. mm
1000 sq. mm
57癈/W
1000 sq. mm
0
1000 sq. mm
60癈/W
* Tab of device attached to topside copper
For the LT1123 the tab is ground so that plated through
holes can be used to couple the tab both electrically and
thermally to the ground plane layer of the board. This will
help to lower the thermal resistance.
Thermal Limiting
The thermal limit of the LT1123 can be used to protect both
the LT1123 and the PNP pass transistor. This is accom-
plished by thermally coupling the LT1123 to the power
transistor. There are clip type heat sinks available for the
TO-92 package that will allow the LT1123 to be mounted
to the same heat sink as the PNP pass transistor. One
example is manufactured by IERC (part #RUR67B1CB).
The LT1123 should be mounted as close as possible to the
Figure 8. Power in R
D
V
IN
(V)
6
8
1k
LT1123 F08
10
100
7
15
14
13
12
11
10
9
5
1W
0.5W
0.25W
2W
APPLICATIO S I FOR ATIO
U
U
U
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