SAF-TE Module
3-39
3.4.3 Interrupts
The LSI53C040 block diagram, Figure 2.1 in the
LSI53C040 Enclosure
Services Processor Technical Manual
, illustrates the primary elements of
the chip: 80C32 microcontroller, DMA core, SCSI core, 8067 core,
SRAM, dual TWS interfaces. In addition to these components, the
LSI53C040 contains several timer registers and access to multipurpose
I/O (MPIO) lines. The 80C32 microcontroller core has six interrupt
sources: Timer 0, Timer 1, Timer 2, Serial Port, External 0, and
External 1. These interrupt sources are controlled by writes to the
Special Function Registers (SFR). The latter two interrupt sources,
External 0 and External 1, provide the means by which interrupts from
the other elements in the LSI53C040 chip can be processed.
The LSI53C040 provides three registers to route interrupts to one of the
two external interrupts. A bit in the Interrupt Status Register (Program
Tag INT_STATUS, 0xFE04) will go high when an interrupt of the
appropriate type is pending. The Interrupt Mask Register (Program Tag
INT_MASK, 0xFE0D) can be used to prevent an interrupt from being
seen (and therefore processed) by the microcontroller core. The Interrupt
Destination Register (Program Tag INT_DESTINATION, 0xFE0E) can be
used to route any of the interrupts to External Interrupt 0 or External
Interrupt 1. The SAF-TE source code disables all interrupts except SCSI
and DMA, and routes these to External Interrupt 1 and 0 respectively. As
implemented, the 80C32 microcontroller processes the following
interrupts as shown in
Table 3.13
.
Table 3.13
Interrupts Processed by 80C32 Microcontroller
Interrupt
Pin
Vector
Address
safte.c
0
0x0003
External 0 (mapped to DMA Interrupts, if enabled)
1
0x000B
Timer 0 (SFRs 0x88–0x8A and 0x8C)
2
0x0013
External 1 (mapped to SCSI Interrupts)
3
0x001B
Timer 1 (SFR 0x88, 0x89, 0x8B, and 0x8D)
4
0x0023
Serial Port (SFR 0x98)
5
0x002B
Timer 2 (SFRs 0xC8, 0xCA–0xCD)