參數(shù)資料
型號: LSI53C860
英文描述: LSI53C860 PCI to Ultra SCSI I/O Processor technical manual v2.1 4/01
中文描述: LSI53C860 PCI到超的SCSI I / O處理器技術(shù)手冊2.1 4 / 01
文件頁數(shù): 152/166頁
文件大?。?/td> 1330K
代理商: LSI53C860
A-6
LSI53C040 Board Utilities
In
config.exe
, enable the code load option and specify that the default
EEPROM is at address E on bus 1. The active (first) firmware is to be
stored on bus 1, chip address E, with beginning address of 4186
(0x105A) and maximum length of 12192 bytes. The inactive (second)
image is to be stored on bus 0, chip address E, with beginning address
of 0 and maximum length of 12192 bytes. (The boot code limits the
firmware to a maximum size of 0x2FA0 or 12912 bytes.)
Create
boot.hex
and
firmware.hex
(Step 3 above).
Download the active image (suppress the header and specify the hex
address):
c:\> cl_isa –b1 –cE –h –a105A firmware.hex
Download the boot image:
c:\>cl_isa –b1 –cE boot.hex
With this configuration, the boot code is located in addresses 0x0000
through 0x1059 and the firmware is at addresses 0x105A through
0x4000. (The boot code limits the firmware to have a maximum size of
0x2FA0 or 12912 bytes). Upon a reset, the firmware is downloaded into
program memory and executed. If
cl_scsi
is executed, the new firmware
will be placed in the EEPROM on bus 1 at address 6.
A.1.4 8067 Utilities
Currently, there are no 8067 utilities available.
A.1.5 LSI53C040 Board Layout/Jumper Settings
The LSI53C040 board contains two banks of switches or jumpers that
specify the behavior of the board hardware.
0
start 1
12192
length 1
Table A.4
Configuration Using Two Serial EEPROMS (Cont.)
The tail of the file
myInput.txt
contains this data:
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