參數(shù)資料
型號: LSI53C1020
英文描述: LSI53C1020 PCI-X to Ultra320 SCSI Controller technical manual v2.0 6/02
中文描述: LSI53C1020 PCI - X到Ultra320 SCSI控制器的技術(shù)手冊2.0 6月2日
文件頁數(shù): 81/166頁
文件大?。?/td> 1330K
代理商: LSI53C1020
SAF-TE Module
3-33
3.4.2.3 Firmware Update
To upload new firmware to the serial EEPROM, which is attached to the
LSI53C040 chip by using a TWS bus, requires that the
CODE_LOAD_ENABLED
option be set during compilation of the
SAF-TE source code. A successful upload of new firmware requires:
Step 1.
Transfer of the new firmware using the SCSI bus to the external
data memory on the LSI53C040 board.
Step 2.
Transfer of the firmware from the external data memory over
the TWS bus to the serial EEPROM.
Step 3.
Error verification.
Step 4.
Updating of the serial EEPROM tables.
Step 5.
LSI53C040 chip reset.
Target Operations during a Code Load
Uploads of code to the serial EEPROM consist of a SCSI transfer
between the Host and the Target’s external memory followed by multiple
transfers from external memory through the TWS bus to the EEPROM.
The global variables are
cl_status
,
cl_addr
, and
cl_byte_count
. These
variables contain the control information used to pass data from the SCSI
code load subroutine (
do_code_load
)
to the background process that
transfers data over the TWS bus (
background_code_load
). The
variables are described below:
cl_status
specifies the (current) status of the TWS bus. See
Table 3.9
.
cl_addr
is the EEPROM address to write the data. Set to the
address in bytes 4 & 5 of a Mode 4 write buffer CDB
(
do_code_load
)
. See
Table 3.10
.
cl_byte_count
is the number of bytes to write to the EEPROM or
the action to implement. The values of this variable and the resulting
action are listed in
Table 3.11
.
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