參數(shù)資料
型號: LS7366R
廠商: LSI Corporation
元件分類: 通用總線功能
英文描述: 32-BIT QUADRATURE COUNTER WITH SERIAL INTERFACE
中文描述: 32位正交計數(shù)器串行接口
文件頁數(shù): 5/13頁
文件大?。?/td> 101K
代理商: LS7366R
DC Electrical Characteristics
. (T
A
= -25C to +85°C)
Parameter Symbol Min. TYP Max. Unit Remarks
Supply Voltage V
DD
3.0
Supply Current
I
DD
300
I
DD
700
Input Voltages
f
CKi
, Logic high
V
CH
2.3
V
CH
3.7
f
CKi
, Logic Low
V
CL
-
V
CL
-
All other inputs, Logic High
V
AH
2.1
V
AH
3.5
-
400
800
5.5
450
950
V
μA
μA
-
V
DD
= 3.0V
V
DD
= 5.0V
-
-
-
-
-
-
-
-
0.7
1.3
V
V
V
V
V
V
V
DD
= 3.0V
V
DD
= 5.0V
V
DD
= 3.0V
V
DD
= 5.0
V
DD
= 3.0V
V
DD
= 5.0V
All other inputs, Logic Low
V
AL
V
AL
-
-
-
-
0.5
1.0
V
V
V
DD
= 3.0V
V
DD
= 5.0V
Input Currents
:
CNT_EN Low
I
IEL
I
IEL
-
- 10.0 15.0
3.0
5.0
μA
μA
V
AL
= 0.7V, V
DD
= 3.0V
V
AL
= 1.2V, V
DD
= 5.0V
CNT_EN High
I
IEH
I
IEH
-
-
-
-
1.0
4.0
0
3.0
6.0
0
μA
μA
μA -
V
AH
= 1.9V, V
DD
= 3.0V
V
AH
= 3.2V, V
DD
= 5.0V
All other inputs, High or Low
Output Currents:
LFLAG, DFLAG Sink
LFLAG Source
DFLAG Source
I
OFL
-1.3 -2.0
I
OFL
-3.2 -4.0
-
0
I
OFH
1.0
I
OFH
2.8
-
-
-
-
-
mA
mA
mA Open Drain Output
mA V
OUT
= 2.5V, V
DD
= 3.0V
mA
V
OUT
= 4.5V, V
DD
= 5.0V
V
OUT
= 0.5V, V
DD
= 3.0V
V
OUT
= 0.5V, V
DD
= 5.0V
0
1.8
3.6
f
CKO
Sink
f
CKO
Source
TXD/MISO:
Sink
I
OCL
-1.3 -2.0
I
OCL
-3.2 -4.0
I
OCH
1.3
I
OCH
3.2
-
-
-
-
mA
mA
mA
mA
V
OUT
= 0.5V, V
DD
= 3.0V
V
OUT
= 0.5V, V
DD
= 5.0V
V
OUT
= 2.5V, V
DD
= 3.0V
V
OUT
= 4.5V, V
DD
= 5.0V
2.0
4.0
I
OML
-1.5 -2.4
I
OML
-3.8 -4.8
-
-
mA
mA
V
OUT
= 0.5V, V
DD
= 3.0V
V
OUT
= 0.5V, V
DD
= 5.0V
Source
I
OMH
1.5
I
OMH
3.8
2.4
4.8
-
-
mA
mA
V
OUT
= 2.5V, V
DD
= 3.0V
V
OUT
= 4.5V, V
DD
= 5.0V
7366R-041906-5
Transient Characteristics
. (T
A
= -25C to +85C, V
DD
= 5V ± 10%)
Parameter Symbol Min. Value Max.Value Unit Remarks
(See Fig. 2)
SCK High Pulse Width
t
CH
100
SCK Low Pulse Width
t
CL
100
SS/ Set Up Time
t
CSL
100
SS/ Hold Time
t
CSH
100
-
-
-
-
-
-
-
-
ns
ns
ns
ns
Quadrature Mode
(See Fig. 5, 7 & 8 )
f
CKI
High Pulse Width
f
CKI
Pulse Width
f
CKI
Frequency
Effective Filter Clock f
F
Period
t
1
t
2
f
FCK
t
3
t
3
f
F
t
4
t
5
f
QA
, f
QB
t
Q1
t
Q2
ti
d
ti
s
ti
h
12
12
-
25
50
-
26
52
-
4t
3
12
32
-
-
4.5t
3
-
-
40
-
-
40
-
-
9.6
5t
3
-
-
5
5
5.5t
3
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
-
ns
ns
ns
ns
ns
-
-
-
t
3
= t
1
+t
2
, MDR0 <7> = 0
t
3
= 2(t
1
+t
2
), MDR0 <7> = 1
f
F
= 1/ t
3
t
4
> t
3
t
5
2
t3
f
QA
= f
QB
< 1/4t
3
-
t
Q2
= (t
3)
/2
t
id
> t
4
-
-
-
Effective Filter Clock f
F
frequency
Quadrature Separation
Quadrature Clock Pulse Width
Quadrature Clock frequency
Quadrature Clock to Count Delay
x1 / x2 / x4 Count Clock Pulse Width
Index Input Pulse Width
Index Set Up Time
Index Hold Time
Quadrature clock to
DFLAG/ or LFLAG/ delay
DFLAG/ output width
t
fl
t
fw
26
-
ns
t
fw
= t
4
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