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參數(shù)資料
| 型號(hào)： | LS7366R |
| 廠商： | LSI Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | 32-BIT QUADRATURE COUNTER WITH SERIAL INTERFACE |
| 中文描述： | 32位正交計(jì)數(shù)器串行接口 |
| 文件頁(yè)數(shù)： | 3/13頁(yè) |
| 文件大小： | 101K |
| 代理商： | LS7366R |
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STR.
The STR is an 8-bit status register which stores
count related status information.
7 6 5 4 3 2 1 0
CY BW CMP IDX CEN PLS U/D S
7366R-122205-3
IR
. The IR is an 8-bit register that fetches instruction bytes from
the received data stream and executes them to perform such
functions as setting up the operating mode for the chip (load the
MDR) and data transfer among the various registers.
B7 B6 B5 B4 B3 B2 B1 B0
B2 B1 B0 = XXX (Don’t care)
B5 B4 B3 = 000: Select none
= 001: Select MDR0
= 010: Select MDR1
= 011: Select DTR
= 100: Select CNTR
= 101: Select OTR
= 110: Select STR
= 111: Select none
B7 B6 = 00: CLR register
= 01: RD register
= 10: WR register
= 11: LOAD register
The actions of the four functions, CLR, RD, WR and LOAD are elaborated in Table 1.
TABLE 1
Number of Bytes
OP Code Register
Operation
Clear MDR0 to zero
Clear MDR1 to zero
None
Clear CNTR to zero
None
Clear STR to zero
Output MDR0 serially on TXD (MISO)
Output MDR1 serially on TXD (MISO)
None
Transfer CNTR to OTR, then output OTR serially
on TXD (MISO)
Output OTR serially on TXD (MISO)
Output STR serially on TXD (MISO)
Write serial data at RXD (MOSI) into MDR0
Write serial data at RXD (MOSI) into MDR1
Write serial data at RXD (MOSI) into DTR
None
None
None
None
None
None
Transfer DTR to CNTR in “parallel”
Transfer CNTR to OTR in “parallel”
MDR0
MRD1
DTR
CNTR
OTR
STR
MDR0
MDR1
DTR
CNTR
1
CLR
2 to 5
RD
OTR
STR
MDR0
MDR1
DTR
CNTR
OTR
STR
MDR0
MDR1
DTR
CNTR
OTR
2 to 5
WR
1
LOAD
CNTR.
The CNTR is a software configurable 8, 16, 24 or 32-bit up/down counter which counts the up/down pulses resulting from
the quadrature clocks applied at the A and B inputs, or alternatively, in non-quadrature mode, pulses applied at the A input.
By means of IR intructions the CNTR can be cleared, loaded from the DTR or in turn, can be transferred into the OTR.
OTR.
The OTR is a software configuration 8, 16, 24 or 32-bit register which can be read back on the MISO output.
Since instantaneous CNTR value is often needed to be read while the CNTR continues to count, the OTR serves as a
convenient dump site for instantaneous CNTR data which can then be read without interfering with the counting process.
CY: Carry (CNTR overflow) latch
BW: Borrow (CNTR underflow) latch
CMP: Compare (CNTR = DTR) latch
IDX: Index latch
CEN: Count enable status: 0: counting disabled,
1: counting enabled
PLS: Power loss indicator latch; set upon power up
U/D: Count direction indicator: 0: count down, 1: count up
S: Sign bit. 1: negative, 0: positive
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