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參數(shù)資料
| 型號： | LS7166-DIP |
| 英文描述： | Peripheral IC |
| 中文描述： | 外圍芯片 |
| 文件頁數(shù)： | 3/3頁 |
| 文件大?。?/td> | 166K |
| 代理商： | LS7166-DIP |
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phone: 360.260.2468
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sales: 800.736.0194
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fax: 360.260.2469
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website: www.usdigital.com
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vancouver, washington 98682 USA
LS7166
Encoder to Microprocessor Interface Chip
Chips
Defines the operating mode of this chip. Select this register by making bit-6
high and bit-7 low.
Bits 0, 1 & 2:
These bits must be reset low for normal operation.
Bit-3:
Reset low to disable the A & B inputs. Set high to enable the A & B inputs.
Bit-4:
The function of hardware pin 4 is defined by this bit. When bit-4 is low,
a low level on pin 4 will reset the 24-bit counter. When bit-4 is high, a high
level on pin 4 will disable the A & B inputs.
Bit-5:
The function of hardware pin 3 is defined by this bit. When bit-5 is low,
a low level on pin 3 will transfer the contents of the 24-bit Preset Register
to the 24-bit Counter.
When bit-5 is high, a low level on pin 3 will transfer to contents of the 24-bit
Counter to the 24-bit Counter Output Latch.
Selects the quadrature count mode. Select this register by making bit-6 high
and bit-7 high. It can be programmed to generate one clock once per
quadrature cycle, once per 1/2 cycle or once per 1/4th cycle (X1, X2 or X4
mode). For example, a 500 cycle/rev encoder can provide 500, 1000 or 2000
counts/rev.
Bits-0 & 1:
Bit-1
Bit-0
Quadrature Count Mode
0
0
Not valid
0
1
X1 mode
1
0
X2 mode
1
1
X4 mode
Bits-3 & 5:
These bits do not matter.
Writing to 1 of the 4 Control Registers:
Set Control/Data high. Bits 6 &
7 are used as address bits to select one of these 4 registers. Only bits 0-5
are stored.
Notes:
D7 & D6 are the Most significant bits of the data bus.
C/D is Control/Data pin 18. RD is Read pin 19. WR is Write pin 1. CS is Chip
Select pin 2. X means "don't care".
Write Cycle Timing:
Allow at least 15ns setup time for valid data, Chip
Select and Control/Data before asserting Write. Make the write pulse at least
60ns long. Hold the data bus, Chip Select and Control/Data stable at least 50ns
after deasserting Write.
Read Cycle Timing:
The data bus will become valid within 110ns after
asserting Chip Select, Control/Data and Read.
The 24-bit Preset Register is the input port for the 24-bit counter. The data
is first written into the Preset Register in 3 write cycles (least significant byte
1st). The address pointer is automatically incremented with each write cycle.
Sequence:
Reset the address pointer by setting bit-0 of the Master Control Register
high.
Load byte 0 (LSB) into this register & increment address
Load byte 1 into this register & increment address
Load byte 2 (MSB) into this register & increment address
Transfer the 3-byte Preset Register to the 24-bit counter by setting bit-3 high
of the Master Control Register.
Preset Register (Write only, Data):
Input Control Register (Write only):
Quadrature Control Register (Write only):
Register Access:
The 24-bit counter value at any instant can be accessed by transferring its
contents to the 24-bit Counter Output Latch. Note that only good stable data
will be passed from the counter to the Output Latch even if the counter bits
are in the midst of a transition. This chip will internally stretch the latch pulse
if necessary until the counter has stabilized. The 3 bytes are then read from
the Output Latch (least significant byte 1st). The address pointer is automati-
cally incremented with each read cycle.
Sequence:
Reset the Address Pointer and transfer the Counter value to the Output
Latch by setting bits 0 and 1 of the Master Control Register high. These bits
will automatically reset to zero after the Read Sequence.
Read byte 0 (LSB) and increment address
Read byte 1 and increment address
Read byte 2 (MSB) and increment address
Counter Output Latch (Read only, Data):
Performs register reset and load operations. Select this register by making
bits 6 and 7 low. Writing a non-zero byte to this register does not require a
follow-up write of an all-zeros byte to terminate an operation. Control
functions may be combined.
All bits are high true.
Bit-0:
Reset the 3-byte Address Pointer, in preparation for a 3-byte (24-bit)
write sequence of the Preset Register or read sequence of the Output Latch.
Bit-1:
Transfer the 24-bit Counter contents to the 24-bit Output Latch.
Bit-2:
Reset the 24-bit Counter, the Borrow Toggle Flip-Flop and the Carry
Toggle Flip-Flop and set the Sign bit high.
Bit-3:
Transfer the 24-bit Preset Register to the 24-bit Counter.
Bit-4:
Reset the Comparator Match Toggle Flip-Flop.
Bit-5:
Master Reset. Reset the 24-bit Counter, the Input Control Register, the
Output Control Register, the Quadrature Register, the Borrow Toggle Flip-
Flop, the Carry Toggle Flip-Flop, the Comparator Toggle Flip-Flop and the 3-
byte address pointer. Note: Master reset does not reset the counter perfectly.
The counter will be either 1, 0 or -1 after a master reset. To reliably reset the
counter to 0, do a Reset Counter Command with bit-2 as shown above.
Master Control Register (Write only):
D7
X
0
0
1
1
X
D6 C/D RD WR CS
X
X
X
0
1
1
1
1
1
0
1
1
1
1
1
X
0
1
Function
Disable Chip for Read or Write
Write to Master Control Register
Write to Input Control Register
Write to Output Control Register
Write to Quadrature Control Register
Write to Preset Register,
then increment Address Counter
Read Output Latch,
then increment Address Counter
Read Output Status Register
X
1
0
0
0
0
0
X
X
0
1
0
X
X
1
1
0
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相關代理商/技術參數(shù) |
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| LS7183N | 制造商:LSI 制造商全稱:LSI 功能描述:QUADRATURE CLOCK CONVERTER |
| LS7184 | 制造商:LSI 制造商全稱:LSI 功能描述:QUADRATURE CLOCK CONVERTER |
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