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參數(shù)資料
| 型號： | LS7166-DIP |
| 英文描述： | Peripheral IC |
| 中文描述： | 外圍芯片 |
| 文件頁數(shù)： | 2/3頁 |
| 文件大?。?/td> | 166K |
| 代理商： | LS7166-DIP |
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2
phone: 360.260.2468
l
sales: 800.736.0194
l
fax: 360.260.2469
email: sales@usdigital.com
l
website: www.usdigital.com
11100 ne 34th circle
l
vancouver, washington 98682 USA
LS7166
Encoder to Microprocessor Interface Chip
Chips
4 useful bits. Initializes the 24-bit Counter and sets operating modes. Select
this register by making bit-6 low and bit-7 high. Control functions may be
combined.
Bit-0:
Low level selects binary count mode. High level selects BCD count
mode.
Bit-1:
This bit must be reset low for normal operation.
Bit-2:
Low level selects normal wrap-around count mode. High level selects
divide-by-N mode (24-bit counter is reloaded from the Preset Register upon
Carry or Borrow).
Bit-3:
This bit must be reset low for normal operation.
Bits 4 & 5:
The functions of hardware pins 16 & 17 are defined by these two
bits. Pin 16 can be defined as any of the following:
Bit-5
Bit-4
Pin 16 Function
0
0
Carry - low true
0
1
Carry toggle flip flop (starts out low)
1
0
Carry - high true
1
1
24-bit Comparator/Counter match - low true
Pin 17 is also defined the the same two bits as follows:
Bit-5
Bit-4
Pin 17 Function
0
0
Borrow - low true
0
1
Borrow toggle flip flop (starts out low)
1
0
Borrow - high true
1
1
24-bit Comparator/Counter match - high true
Output Control Register (Write only):
Readtime Hardware Output Pin Description:
Carry or Match (Output) (Pin 16):
The function of this pin is defined by bits 4 and 5 of the Output Control Register
as follows:
Bit-5
Bit-4
Pin Function
0
0
Carry - low true
0
1
Carry toggle flip flop (starts out low)
1
0
Carry - high true
1
1
24-bit Comparator / Counter match - low true
Borrow or Match (Output) (Pin 17):
The function of this pin is also defined by bits 4 and 5 of the Output Control
Register as follows:
Bit-5
Bit-4
Pin Function
0
0
Borrow - low true
0
1
Borrow toggle flip flop (starts out low)
1
0
Borrow - high true
1
1
24-bit Comparator/Counter match - high true
Note that the functions of pins 16 and 17 are defined by the same 2 bits of
the Output Control Register. They are inseparably linked together.
The toggle flip flops are triggered by the trailing edges of the associated Carry,
Borrow, or Compare match. Thus there is a 1-clock delay between the input
and output of each flip flop.
Unless otherwise specified, assume the longest prop delay from any input
to any output is <110ns.
Bits 5, 6 and 7
are always high.
Bit-0:
Borrow Toggle Flip-Flip. Toggles every time the 24-bit counter
underflows generating a borrow.
Bit-1:
Carry Toggle Flip-Flip. Toggles every time the 24-bit counter overflows
generating a carry. Trailing edge triggered.
Bit-2:
Compare Toggle Flip Flop. Toggles every time the 24-bit counter equals
the 24-bit Preset Register. Trailing edge triggered.
Bit-3:
Sign bit. Set low when a Borrow occurs. Set high when a Carry occurs.
Level triggered.
Bit-4:
Up/Down Counter Direction. Reset low when counting down, Set high
when counting up. Leading edge triggered.
Bits 5, 6 and 7
are always high.
Status Register (Read only, Control):
Parameter
Supply voltage
Supply current
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Input current
Output source current
Output sink current
Data bus off-state
Leakage current
Min.
4.5
-
-
2.0
-
2.5
-
200
4
Max.
5.5
200
0.8
-
0.4
-
15
-
-
Units
Volts
μA
Volts
Volts
Volts
Volts
nA
μA
mA
Notes
@ 5.0V
@4mA sink
@200μA source
leakage current
@V
OH
= 2.5V
@V
OL
= 0.4V
-
15
nA
A & B (Inputs) (Pins 6 & 7):
Connect to A & B quadrature outputs of the encoder. The quadrature code
will be decoded and used to clock and steer the 24-bit Counter. It can be
programmed to generate one clock once per quadrature cycle, once per 1/
2 cycle or once per 1/4th cycle (X1, X2 or X4 mode). Maximum count
frequency is 10 MHz.
A/B Enable or Counter Reset (Input) (Pin 4):
Active low. Minimum low pulse width is 60ns. The function of this pin is defined
by bit-4 of the Input Control Register. When bit-4 is low, a low level on this
pin will reset the 24-bit counter. When bit-4 is high, a low level on this pin will
enable the A & B inputs.
Load Counter or Load Latch (Input) (Pin 3):
Active low. Minimum low pulse width is 60ns. The function of this pin is
defined by bit-5 of the Input Control Register. When bit-5 is low, a low level
on this pin will transfer the contents of the 24-bit Preset Register to the 24-
bit Counter. When bit-5 is high, a low level on this pin will transfer the contents
of the 24-bit Counter to the 24-bit Counter Output Latch.
Realtime Hardware Input Pin Descriptions:
Data Bus (Pins 8-15):
Three-state, 8-bits. Used to pass data to and from the internal registers in
single and multiple-byte transfers. Bits 6 & 7 are used as address bits to select
the desired control registers during write operations.
Chip Select (Input) (Pin 2):
Active Low, enables the chip to Read or Write on the data bus.
Read (Input) (Pin 19):
Active Low, enables the Status Register or 1-byte of the 24-bit Output Latch
to be read on the data bus.
Write (Input) (Pin 1):
Active Low, during chip select, latches the data bus into the internal registers.
Control-Hi/Data-Lo (Input) (Pin 18):
Used to address various resistors during read and write cycles. A high level
during a read cycle selects the Status Register. A high level during a write
cycle selects 1 of the 4 Control Registers. A low level during a write cycle
selects one byte of the Preset Register. A low level during a read cycle
selects one byte of the Counter Output Latch.
Microprocessor Bus Pin Descriptions:
DC Electrical Characteristics:
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