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參數(shù)資料
| 型號(hào)： | LS7062 |
| 廠(chǎng)商： | LSI Corporation |
| 元件分類(lèi)： | 通用總線(xiàn)功能 |
| 英文描述： | 32 BIT/DUAL 16 BIT BINARY UP COUNTER WITH BYTE MULTIPLEXED THREE-STATE OUTPUTS |
| 中文描述： | 32位/雙16位與字節(jié)二元復(fù)三項(xiàng)反態(tài)輸出 |
| 文件頁(yè)數(shù)： | 3/7頁(yè) |
| 文件大?。?/td> | 64K |
| 代理商： | LS7062 |
DYNAMIC ELECTRICAL CHARACTERISTICS:
(V
DD
= +5V ± 5%, V
SS
= 0
V
, T
A
= 0C to +70C unless otherwise noted.)
PARAMETER
SYMBOL
Count Frequency
fc
(All Count inputs)
Count Pulse Width
t
CPW
(All Count Inputs)
MIN
DC
MAX
15
UNIT
MHz
CONDITIONS
-
30
-
ns
Measured at 50% point,
Max tr, t
f
= 10ns
Count Rise & Fall time
(Pins 1, 13)
tr, tf
-
30
μs
-
Count Ripple Time
(Pins 1, 2 - LS7062)
t
CR
-
4
μs
Transition from 32 ones to 32 zeros
from negative edge of count pulse
Count Ripple Time
(Pin 13 - LS7060)
(Pins 1,2,13 - LS7062)
Reset Pulse Width
(All Counter Stages
Fully Reset)
t
CR
-
2
μs
Transition of 16 bits from
all ones to all zeros from negative edge
of count pulse
Measured at 50% point
Max t
r
, t
f
= 200ns
t
RPW
500
-
ns
RESET Removal Time
(Reset Removed From
All Counter Stages)
t
RR
-
250
ns
Measured from RESET signal at V
IH
SCAN Frequency
SCAN Pulse Wildth
f
SC
t
SCPW
-
1
-
MHz
ns
500
Measured at 50% point
Max t
r
, t
f
= 100ns
Measured at 50% point
Max t
r
, t
f
= 200ns
SCAN RESET/LOAD
Pulse Width
(All latches loaded and
Scan Counter Reset to
Least Significant Byte)
t
RSCPW
1
-
μs
SCAN RESET/LOAD
Removal Time
(Reset Removed from
Scan Counter; Load
Command Removed
From Latches)
t
RSCR
-
250
ns
Measured from SCAN RESET/
LOAD at V
IH
Output Disable
Delay Time
(B0 - B7)
t
DOD
-
200
ns
Transition to Output High
Impedance State Measured
From Scan at V
IL
or
ENABLE at V
IH
Transition to Valid On State
Measured from Scan at V
IH
and ENABLE at V
IL
; Delay to
Valid Data Levels for C
OL
=10pF
and one TTL Load or Valid Data
Currents for High Capacitance Loads
Negative Transition from Scan at V
IL
and ST5 of Scan Counter or Positive
Transition From SCAN RESET/LOAD at
V
IL
to Valid Data Levels for C
OL
= 10pF
and one TTL Load
Output ENABLE
Delay Time
(B0 - B7)
t
DOE
-
200
ns
Output Delay Time
CASCADE ENABLE
t
DCE
-
300
ns
INPUT CURRENT
*SCAN RESET/LOAD
I
IH
I
IL
I
IH
I
IL
-
-
-
-
-2.5
-5
5
1
μA
μA
μA
μA
V
DD
= Max, V
IH
= +3.5
V
DD
= Max, V
IL
= 0
V
DD
= Max, V
IH
= +3.5
V
DD
= Max, V
IL
= 0
**All Count inputs
*Input has internal pull-up resistor to V
DD
** Inputs have internal pull-down resistor to V
SS
7060/62-071398-3
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