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參數(shù)資料
| 型號： | LS7062 |
| 廠商： | LSI Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | 32 BIT/DUAL 16 BIT BINARY UP COUNTER WITH BYTE MULTIPLEXED THREE-STATE OUTPUTS |
| 中文描述： | 32位/雙16位與字節(jié)二元復(fù)三項反態(tài)輸出 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 64K |
| 代理商： | LS7062 |
32 BIT/DUAL 16 BIT BINARY UP COUNTER
WITH BYTE MULTIPLEXED THREE-STATE OUTPUTS
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L
PIN ASSIGNMENT - TOP VIEW
SCAN
ENABLE
SCAN RESET/LOAD
TEST COUNT
B7 OUT
B6 OUT
B5 OUT
B4 OUT
V
DD
(+V)
ALT COUNT
B3 OUT
B2 OUT
B1 OUT
B0 OUT
RESET
CASCADE EN OUT
V
SS
(-V)
FIGURE 1
LS7060
COUNT
FEATURES:
DC to 15 MHz Count Frequency
Byte Multiplexer
DC to 1 MHz Scan Frequency
+4.75V to +5.25V Operation (V
DD
-V
SS
)
Three-State Data Outputs, Bus and TTL Compatible
Inputs TTL and CMOS Compatible
Unique Cascade Feature Allows Multiplexing of
Successive Bytes of Data in Sequence in Multiple
Counter Systems
Low Power Dissipation
LS7060, LS7062 (DIP); LS7060-S, LS7062-S (SOIC)
See Figures
1 and 2
DESCRIPTION:
The LS7060/LS7062 is a monolithic, ion implanted MOS Silicon
Gate, 32 bit/dual 16 bit up counter. The IC includes latches, multi-
plexer, eight three-state binary data output drivers and output
cascading logic.
DESCRIPTION OF OPERATION:
32 (16) BIT BINARY UP COUNTER - LS7060 (LS7062)
The 32(16) bit static ripple through counter increments on the
negative edge of the input count pulse. Maximum ripple time is
4μs (2μs) - transition count of 32(16) ones to 32(16) zeros.
Guaranteed count frequency is DC to 15MHz.
See Figure 9A(9B) for Block Diagram.
COUNT, ALT COUNT
(LS7060)
Input count pulses to the 32 bit counter may be applied through
either of these two inputs. The ALT COUNT input circuitry con-
tains a Schmitt trigger network which allows proper counting with
"infinitely" long clock edges. A high applied to either of these two
inputs inhibits counting.
COUNT A, ALT COUNT A
(LS7062)
Input count pulses to the first 16 bit counter may be applied
through either of these two inputs. The ALT COUNT A input cir-
cuitry contains a Schmitt trigger network which allows proper
counting with “infinitely” long clock edges. A high applied to either
of these two inputs inhibits counting.
RESET
All 32 counter bits are reset to zero when RESET is brought low
for a minimum of 1μs. RESET must be high for a minimum of
300ns before next valid count can be recorded.
TEST COUNT
(LS7060)
Count pulses may be applied to the last 16 bits of the binary
counter through this input, as long as Bit 16 of the counter is a
low. The counter advances on the negative transition of these
pulses. This input is intended to be used for test purposes.
July 1998
7060/62-071698-1
LSI/CSI
UL
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405
LS7060/7062
COUNT B
(LS7062)
Count pulses may be applied to the last 16 bits of the binary
counter through this input. The counter advances on the neg-
ative transition of these pulses.
LATCHES -
LS7060 (LS7062)
32 bits of latch are provided for storage of counter data. All latch-
es are loaded when the LOAD input is brought low for a mini-
mum of 1μs and kept low until a minimum of 4μs (2μs) has
elapsed from previous negative edge of count pulse (ripple time).
Storage of valid data occurs when LOAD is brought high for a
minimum of 250ns before next negative edge of count pulse or
RESET.
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17
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L
PIN ASSIGNMENT - TOP VIEW
SCAN
ENABLE
SCAN RESET/LOAD
COUNT B
B7 OUT
B6 OUT
B5 OUT
B4 OUT
V
DD
(+V)
ALT COUNT A
B3 OUT
B2 OUT
B1 OUT
B0 OUT
RESET
CASCADE EN OUT
V
SS
(-)
FIGURE 2
LS7062
COUNT A
A3800
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