參數(shù)資料
型號(hào)： LR38603
廠商： Sharp Corporation
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processor for Color CCD Cameras
中文描述： 數(shù)字信號(hào)處理器的彩色CCD相機(jī)
文件頁(yè)數(shù)： 7/26頁(yè)
文件大?。?/td> 160K
代理商： LR38603
LR38603
7
DSP REGISTER TABLE
ADDRESS
00h
01h
NAME
BIT
[7 : 0] Stop reading from EEPROM only when EEPROM data is FF.
[7]
H : Luminance signal processing without LPF (when using B/W CCD)
[6 : 5] 00 : 270 k pixel CCD (NTSC) 01 : 410 k pixel CCD (NTSC)
10 : 320 k pixel CCD (PAL) 11 : 470 k pixel CCD (PAL)
[4 : 3] Input data timing adjustment
00 : Reference 01 : 1 clock delay 10 : 1 clock forward 11 : 2 clocks forward
[2]
1 : Latch with inverted clock
[1 : 0] Fixed to 1X (IR3Y48A1)
[6]
0 : Interlace 1 : Non-interlace
Select output mode.
000 : Analog video output
EXCKI : Vertical reset pulse input
001 : Analog video output
EXCKI : 8 fsc clock input
EEMD
2
: Horizontal reset pulse input
010 : Analog video output
EEMD
2
: Horizontal reset pulse input
EEMD
3
: Vertical reset pulse input
100 : YUV digital video output : Clock rate of video data pixel-CK
101 : YUV digital video output : Clock rate of video data EXCKI
110 : UYVY digital video output : Clock rate of video data EXCKI
011, 111 are prohibited.
[2]
Shutter speed at power-on
0 : minimum
[1]
PGA control
0 : Auto
[0]
Carrier balance control
0 : Auto
[6 : 5] Select output signal from HD pin
00 : HD output (CCD drive timing) 01 : HD output (video output timing)
10 : BELL pulse (in analog video output), HREF (in digital video output)
11 : Fixed to L level
[4 : 3] Select output signal from VD pin
00 : VD output (CCD drive timing) 01 : VD output (video output timing)
10 : Fixed to L level (in analog video output), VS (in digital video output)
11 : Fixed to L level (in analog video output), CSYNC (in digital video
output)
[2 : 1] Select output signal from DCK
1
pin (in analog video output)
00 : CSYNC 01 : CBLNK 1X : Fixed to L level
[0]
Select output signal from DCK
2
pin (in analog video output)
0 : Fluorescent signal 1 : Fixed to L level
[7 : 0] Electronic shutter control (EEMDS, EEMD
1
, EEME
2
, EEMD
3
), mirror video
output (MIR [MSB]), internal register for exposure-standard (BLC) and white
balance (WB
2
, WB
1
[LSB]) are set when selecting digital output mode with
MODE_OUT_SIG (address 02h).
Shutter control of EEMD
2
and EEMD
3
is set by the register of SW_CTRL
and that of EEMDS and EEMD
1
is set by pin 41 and pin 42 when setting
"001" and "010" with MODE_OUT_SIG (address 02h).
CONTENTS
STOP_EEPROM
LPF_TH
CCD_SEL
ADTI
SEL_CDS
NI
MODE_OUT_SIG
02h
[5 : 3]
EEMD
3
: Vertical reset pulse input
START_EE
AGC_FIX
OB_SEL
HD_SEL
1 : maximum
1 : Fixed
1 : Fixed
03h
VD_SEL
DCK1_SEL
DCK2_SEL
04h
SW_CTRL
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