參數(shù)資料
型號(hào)： LR38603
廠商： Sharp Corporation
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processor for Color CCD Cameras
中文描述： 數(shù)字信號(hào)處理器的彩色CCD相機(jī)
文件頁(yè)數(shù)： 13/26頁(yè)
文件大?。?/td> 160K
代理商： LR38603
LR38603
13
ADDRESS
7Dh
7Eh
7Fh
80h
NAME
BIT
[6 : 0] Suppression level of horizontal edge signal.
[4 : 0] Initial value of APT_VGA (gain of vertical edge signal)
[6 : 0] Suppression level of vertical edge signal.
[7 : 0] Start point of edge signal suppression (PGA gain).
[5 : 0] Gain of edge signal suppression.
[5 : 0] Start point of edge signal suppression in maximum PGA gained luminance.
[7 : 0] Luminance suppression point of high luminance aperture.
[6]
Select level of edge signal, used in internal calculation. 1 : 1/4 times
[5 : 3] Delete timing of horizontal edge : –2 to +2
[2 : 0] Delete timing of vertical edge : –2 to +2
[7 : 0] Difference of 0H, 2H signal allowed level, for judgment of line crawl.
[7 : 0] Difference of R, B signal allowed level, for judgment of line crawl.
CONTENTS
APT_HCL
APT_VGA
APT_VCL
APT_S
APT_H
APT_Y
CKI_HCL2
CKI_ETI
81h
82h
83h
84h
85h
86h
87h
88h
LC_K1
LC_K2
LC_MAX
SETUP
[7 : 0] Judgment of luminance level, for judgment of line crawl.
[6]
Switch CBLK level.
[5 : 0] Adjustment of setup level (complement of 2).
[7]
Sign of burst level R – Y 1 : – direction 0 : + direction
[6 : 0] Burst level R – Y.
[7]
Sign of burst level B – Y 1 : – direction 0 : + direction
[6 : 0] Burst level B – Y (sign + absolute value).
[6]
1 : Mute in encoder.
[5]
1 : Stop adding SYNC to analog output.
[4 : 0] Gain of analog output (1 time at 10h).
[7 : 0] Adjustment of SYNC level.
[7]
1 : Disable output mute at power-on.
[6 : 0] Period of mute (MUTE_OUT x 2 vertical period)
[7]
Switch attribute of FH
[6]
Switch attribute of FR
[5 : 3] ADCK phase adjustment
When using 270 k, 320 k-pixel CCDs 000 : standard to 101 : 300 (delayed
from "000" to "101" every 60.)
When using 410 k, 470 k-pixel CCDs 000 : standard to 101 : 270 (delayed
from "000" to "101" every 45.)
[2 : 0] FS phase adjustment 000 : standard to 111 : 14 ns delay (delayed from
"000" to "111" every 2 ns.)
[7 : 6] FH
2
phase adjustment
00 : standard 01 : 1 ns delay 10 : 2 ns delay 11 : 3 ns delay
[5 : 3] FCDS phase adjustment 000 : standard to 111 : 14 ns delay (delayed from
"000" to "111" every 2 ns.)
[2 : 0] RS phase adjustment 000 : standard to 111 : 14 ns delay (delayed from
"000" to "111" every 2 ns.)
[6]
1 : Standby
[5 : 0] Period of return from standby (STANDBY x vertical period)
89h
BAS_R
8Ah
BAS_B
8Bh
OUTGA
8Eh
SEL_FH
SEL_FR
SEL_ADCK
1 : Inverted
1 : Inverted
8Ch
8Dh
SYNCLEV
MUTE_OUT
SEL_FS
8Fh
SEL_FH2
SEL_FCDS
SEL_RS
90h
STANDBY
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