參數(shù)資料
型號: LR38574
廠商: Sharp Corporation
英文描述: Timing Generator IC for 1 090 k/1 310 k-pixel CCDs
中文描述: 時序發(fā)生器集成電路1 090鉀/ 1 310的k -像素CCD
文件頁數(shù): 4/9頁
文件大?。?/td> 64K
代理商: LR38574
4
LR38574
PIN NO.
SYMBOL
I/O
POLARITY
PIN NAME
DESCRIPTION
20
V
DD3
Power supply
Supply of +3.3 V power.
An input pin for resetting all internal circuits at power on.
Connect to V
DD
through the diode and GND through the
capacitor.
A pulse to sample-hold the signal.
The output phase of RS is selected by serial data.
All clear input
ICU3
ACLX
21
A grounding pin.
An input pin to control internal vertical clock for long
shutter speed.
H level or open
: VD
L level
: VD is masked by the pulse which
is latched at the rising edge of VD.
It's necessary to be set SMD = high and number of the
fields data n ≥ 2 in serial data control at VCON operation.
An input pin for reference clock oscillation.
The frequency is 24.54545 MHz.
An output pin for reference clock oscillation.
The output is the inverse of CKI (pin 25).
An output pin to generate HD and VD pulses.
The frequency is 12.72737 MHz.
An output pin for DSP IC. The frequency is 12.72727 MHz.
The output phase of DCLK is selected by serial data
step by 90.
An input pin for reference of vertical pulse.
Connect to VD pin of DSP IC.
Supply of +3.3 V power.
A grounding pin.
An input pin for reference of horizontal pulse.
Connect to HD pin of DSP IC.
An input pin for the strobe pulse, to control the functions
of LR38574. For details, see
"
Serial Data Control
"
.
An input pin for the clock of the shift register, to control
the functions of LR38574. For details, see
"
Serial Data
Control
"
.
Ground
GND
23
22
RS
O6MA3
S/H pulse output
24
VCON
ICU3
VD control input
A pulse to sample-hold the signal from CCD.
The output phase of FS is selected by serial data.
CDS pulse output 2
O6MA3
FS
19
Clock input
OSCI3
CKI
25
26
CKO
OSCO3
Clock output
Clock output
O6MA3
CLK
27
28
DCLK
O6MA3
Clock output
Vertical reference
pulse input
Power supply
Ground
Horizontal drive
pulse input
IC3
VD
29
30
31
V
DD3
GND
32
HD
IC3
Strobe pulse input
ICSU3
ED
0
33
34
ED
1
ICSU3
Shift register clock
input
18
FCDS
O6MA3
CDS pulse output 1
A pulse to clamp the feed-through level from CCD.
The output phase of FCDS is selected by serial data.
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