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| 型號(hào)： | LPC47S422-MS |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類(lèi)： | 外設(shè)及接口 |
| 英文描述： | ENHANCED SUPER I/O WITH LPC INTERFACE FOR SERVER APPLICATIONS |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP100 |
| 封裝： | LEAD FREE, QFP-100 |
| 文件頁(yè)數(shù)： | 80/264頁(yè) |
| 文件大?。?/td> | 1342K |
| 代理商： | LPC47S422-MS |
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Bit 0
Data Ready (DR). It is set to a logic "1" whenever a complete incoming character has been received and
transferred into the Receiver Buffer Register or the FIFO. Bit 0 is reset to a logic "0" by reading all of the
data in the Receive Buffer Register or the FIFO.
Bit 1
Overrun Error (OE). Bit 1 indicates that data in the Receiver Buffer Register was not read before the next
character was transferred into the register, thereby destroying the previous character. In FIFO mode, an
overrunn error will occur only when the FIFO is full and the next character has been completely received in
the shift register, the character in the shift register is overwritten but not transferred to the FIFO. The OE
indicator is set to a logic "1" immediately upon detection of an overrun condition, and reset whenever the
Line Status Register is read.
Bit 2
Parity Error (PE). Bit 2 indicates that the received data character does not have the correct even or odd
parity, as selected by the even parity select bit. The PE is set to a logic "1" upon detection of a parity error
and is reset to a logic "0" whenever the Line Status Register is read. In the FIFO mode this error is
associated with the particular character in the FIFO it applies to. This error is indicated when the
associated character is at the top of the FIFO.
Bit 3
Framing Error (FE). Bit 3 indicates that the received character did not have a valid stop bit. Bit 3 is set to
a logic "1" whenever the stop bit following the last data bit or parity bit is detected as a zero bit (Spacing
level). The FE is reset to a logic "0" whenever the Line Status Register is read. In the FIFO mode this
error is associated with the particular character in the FIFO it applies to. This error is indicated when the
associated character is at the top of the FIFO. The Serial Port will try to resynchronize after a framing
error. To do this, it assumes that the framing error was due to the next start bit, so it samples this 'start' bit
twice and then takes in the 'data'.
Bit 4
Break Interrupt (BI). Bit 4 is set to a logic "1" whenever the received data input is held in the Spacing state
(logic "0") for longer than a full word transmission time (that is, the total time of the start bit + data bits +
parity bits + stop bits). The BI is reset after the CPU reads the contents of the Line Status Register. In the
FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is
indicated when the associated character is at the top of the FIFO. When break occurs only one zero
character is loaded into the FIFO. Restarting after a break is received, requires the serial data (RXD) to be
logic "1" for at least 1/2 bit time.
Note: Bits 1 through 4 are the error conditions that produce a Receiver Line Status Interrupt whenever
any of the corresponding conditions are detected and the interrupt is enabled.
Bit 5
Transmitter Holding Register Empty (THRE). Bit 5 indicates that the Serial Port is ready to accept a new
character for transmission. In addition, this bit causes the Serial Port to issue an interrupt when the
Transmitter Holding Register interrupt enable is set high. The THRE bit is set to a logic "1" when a
character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. The bit is
reset to logic "0" whenever the CPU loads the Transmitter Holding Register. In the FIFO mode this bit is
set when the XMIT FIFO is empty, it is cleared when at least 1 byte is written to the XMIT FIFO. Bit 5 is a
read only bit.
80
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PDF描述 |
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| LPC47S422QFP | ENHANCED SUPER I/O WITH LPC INTERFACE FOR SERVER APPLICATIONS |
| LPC47U33x | 100 Pin Enhanced Super I/O for LPC Bus with Consumer Features and SMBus Controller |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| LPC47S422QFP | 制造商:Rochester Electronics LLC 功能描述:SUPER 1/O CONTROLLER W/LPC - Bulk |
| LPC47S42X | 制造商:SMSC 制造商全稱(chēng):SMSC 功能描述:ENHANCED SUPER I/O WITH LPC INTERFACE FOR SERVER APPLICATIONS |
| LPC47S457-NC | 功能描述:輸入/輸出控制器接口集成電路 Enhanced Super I/O Controller RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| LPC47S457-NS | 功能描述:接口 - 專(zhuān)用 Enhanced Super I/O Controller RoHS:否 制造商:Texas Instruments 產(chǎn)品類(lèi)型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| LPC47S45X | 制造商:SMSC 制造商全稱(chēng):SMSC 功能描述:Advanced I/O with X-Bus Interface |
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