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參數(shù)資料
| 型號(hào)： | LPC47S422-MS |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | ENHANCED SUPER I/O WITH LPC INTERFACE FOR SERVER APPLICATIONS |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP100 |
| 封裝： | LEAD FREE, QFP-100 |
| 文件頁(yè)數(shù)： | 143/264頁(yè) |
| 文件大?。?/td> | 1342K |
| 代理商： | LPC47S422-MS |
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Bit[5] in the SMI_STS7 register is the status bit and bit[5] in the SMI_EN7 register is the enable bit for
the generation of the SMI when the SLP_EN bit is written to ‘1’. These registers are located at the
address programmed in the Base I/O address in Logical Device A at the offset of 0x64 and 0x66.
See the Runtime Registers section for description on these registers.
PME Support
The LPC47S42x offers support for Power Management Events (PMEs), also referred to as System
Control Interrupt (SCI) events in an ACPI system. A power management event is indicated to the
chipset via the assertion of the nIO_PME signal. In the LPC47S42x, the nIO_PME is asserted by active
transitions on the ring indicator inputs nRI1 and nRI2, active keyboard-data edges, active mouse-data
edges, Wakeup on Specific key, Super I/O Device Interrupts, Watchdog Timer, programmable edges on
GPIO pins and fan tachometer event. The GP42/nIO_PME pin, when selected for the nIO_PME
function, can be programmed to be active high or active low via the polarity bit in the GP42 register.
The output buffer type of the pin can be programmed to be open-drain or push-pull via bit 7 of the GP42
register. The nIO_PME pin function defaults to active low, open-drain output.
PME functionality is controlled by the PME status and enable registers in the runtime registers block,
which is located at the address programmed in configuration registers 0x60 and 0x61 in Logical Device
A. The PME Enable bit, PME_EN, globally controls PME Wake-up events. When PME_EN is inactive,
the nIO_PME signal can not be asserted. When PME_EN is asserted, any wake source whose
individual PME Wake Enable register bit, is asserted can cause nIO_PME to become asserted.
The PME Wake Status register indicates that an enabled wake source has occurred and if the PME_EN
bit is set, asserted the nIO_PME signal. The PME Status bit is asserted by active transitions of PME
Wake sources. PME_STS will become asserted independent of the state of the global PME enable,
PME_EN.
The following pertains to the PME status bits for each event:
The output of the status bit for each event is combined with the corresponding enable bit to set the
PME status bit.
The status bit for any pending events must be cleared in order to clear the PME_STS bit.
For the GPIO events, the polarity of the edge used to set the status bit and generate a PME is
controlled by the polarity bit of the GPIO control register. For non-inverted polarity (default) the status
bit is set on the low-to-high edge. If the EETI function is selected for a GPIO then both a high-to-low and
a low-to-high edge will set the corresponding PME status bits. Status bits are cleared on a write of ‘1’.
The PME Wake registers also include status and enable bits for the fan tachometer input.
See the “Keyboard and Mouse PME Generation” section for information about using the keyboard and
mouse signals to generate a PME.
The P12 and P16 bits enable a PME event on single high-to-low edge or on both high-to-low and low-
to-high edges. Default is single edge. There is also a polarity select bit in the configuration register at
0xF0 in Logical Device 7. The register that selects the edge, Edge Select register, is located at the
address programmed in the Base I/O Address register in the Logical Device A at an offset of 21h. Refer
also to PME Status and Enable register 9. See the Runtime Registers sections for description on these
registers.
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PDF描述 |
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| LPC47S422QFP | ENHANCED SUPER I/O WITH LPC INTERFACE FOR SERVER APPLICATIONS |
| LPC47U33x | 100 Pin Enhanced Super I/O for LPC Bus with Consumer Features and SMBus Controller |
| LPC870-FJ | Mini SIDELED |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| LPC47S422QFP | 制造商:Rochester Electronics LLC 功能描述:SUPER 1/O CONTROLLER W/LPC - Bulk |
| LPC47S42X | 制造商:SMSC 制造商全稱:SMSC 功能描述:ENHANCED SUPER I/O WITH LPC INTERFACE FOR SERVER APPLICATIONS |
| LPC47S457-NC | 功能描述:輸入/輸出控制器接口集成電路 Enhanced Super I/O Controller RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| LPC47S457-NS | 功能描述:接口 - 專用 Enhanced Super I/O Controller RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| LPC47S45X | 制造商:SMSC 制造商全稱:SMSC 功能描述:Advanced I/O with X-Bus Interface |
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