- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358934 > LPC47M14U-NC (SMSC Corporation) Connector assemblies, Mouse Computer cables; Connector Type A:male; Connector Type B:female; Cable Length:10ft PDF資料下載
參數(shù)資料
| 型號： | LPC47M14U-NC |
| 廠商： | SMSC Corporation |
| 英文描述： | Connector assemblies, Mouse Computer cables; Connector Type A:male; Connector Type B:female; Cable Length:10ft |
| 中文描述： | 128引腳ENGANCED超級I / O與LPC接口和USB集線器控制器 |
| 文件頁數(shù)： | 82/205頁 |
| 文件大?。?/td> | 1219K |
| 代理商： | LPC47M14U-NC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁當(dāng)前第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁
SMSC DS – LPC47M14X
Page 82
Rev. 03/19/2001
EPP 1.9 Read
The timing for a read operation (data) is shown in timing diagram EPP Read Data cycle. The chip inserts wait states into
the LPC I/O read cycle until it has been determined that the read cycle can complete. The read cycle can complete
under the following circumstances:
1) If the EPP bus is not ready (nWAIT is active low) when nDATASTB goes active then the read can complete
when nWAIT goes inactive high.
2) If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing
the state of nWRITE or before nDATASTB goes active. The read can complete once nWAIT is determined
inactive.
Read Sequence of Operation
1) The host initiates an I/O read cycle to the selected EPP register.
2) If WAIT is not asserted, the chip must wait until WAIT is asserted.
3) The chip tri-states the PData bus and deasserts nWRITE.
4) Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE
signal is valid.
5) Peripheral drives PData bus valid.
6) Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the
cycle.
7) a) The chip latches the data from the PData bus for the internal data bus and deasserts nDATASTB or
nADDRSTRB. This marks the beginning of the termination phase.
b) The chip drives the sync that indicates that no more wait states are required and drives the valid data onto
the LAD[3:0] signals, followed by the TAR to complete the read cycle.
8) Peripheral tri-states the PData bus and asserts nWAIT, indicating to the host that the PData bus is tri-stated.
9) Chip may modify nWRITE, PDIR and nPDATA in preparation for the next cycle.
EPP 1.7 OPERATION
When the EPP 1.7 mode is selected in the configuration register, the standard and bi-directional modes are also
available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bi-
directional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is
controlled by PCD of the Control port.
In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to
prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP cycle to the end
of the cycle. If a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit 0.
Software Constraints
Before an EPP cycle is executed, the software must ensure that the control register bits D0, D1 and D3 are set to zero.
Also, bit D5 (PCD) is a logic "0" for an EPP write or a logic "1" for and EPP read.
EPP 1.7 Write
The timing for a write operation (address or data) is shown in timing diagram EPP 1.7 Write Data or Address cycle. The
chip inserts wait states into the I/O write cycle when nWAIT is active low during the EPP cycle. This can be used to
extend the cycle time. The write cycle can complete when nWAIT is inactive high.
Write Sequence of Operation
1) The host sets PDIR bit in the control register to a logic "0". This asserts nWRITE.
2) The host initiates an I/O write cycle to the selected EPP register.
3) The chip places address or data on PData bus.
4) Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE
signal is valid.
5) If nWAIT is asserted, the chip inserts wait states into I/O write cycle until the peripheral deasserts nWAIT or a
time-out occurs.
6) The chip drives the final sync, deasserts nDATASTB or nADDRSTRB and latches the data from the internal
data bus for the PData bus.
7) Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LPC47M14W-NC | SNAP LOCK CABLE MARKER - J (10PK) |
| LPC47M14A-NC | 128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M14T-NC | 128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M14S-NC | 128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M192 | LPC SUPER I/O WITH HARDWARE MONITORING BLOCK |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LPC47M14V-NC | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M14W-NC | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M14X | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M14X-NC | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M14Y-NC | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。