- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358934 > LPC47M14U-NC (SMSC Corporation) Connector assemblies, Mouse Computer cables; Connector Type A:male; Connector Type B:female; Cable Length:10ft PDF資料下載
參數(shù)資料
| 型號： | LPC47M14U-NC |
| 廠商： | SMSC Corporation |
| 英文描述： | Connector assemblies, Mouse Computer cables; Connector Type A:male; Connector Type B:female; Cable Length:10ft |
| 中文描述： | 128引腳ENGANCED超級I / O與LPC接口和USB集線器控制器 |
| 文件頁數(shù)： | 122/205頁 |
| 文件大?。?/td> | 1219K |
| 代理商： | LPC47M14U-NC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁當(dāng)前第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁
SMSC DS – LPC47M14X
Page 122
Rev. 03/19/2001
6.18 SECURITY FEATURE
The following register describes the functionality to support security in the LPC47M14x.
6.18.1
GPIO Device Disable Register Control
The GPIO pin GP43 is used for the Device Disable Register Control (DDRC) function. Setting bits[3:2] of the GP43
configuration register to ‘01’, selects the DDRC function for the GP43 pin. When bits[3:2]=01 the GP43 pin is an
input, with non-inverted polarity. Bits[3:2] cannot be cleared by writing to these bits; they are cleared by VTR POR,
VCC POR and Hard Reset. That is, when the DDRC function is selected for this pin, it cannot be changed, except by a
VCC POR, hard reset or VTR POR.
When the DDRC function is selected for GP43, the Device Disable register is controlled by the value of the GP43 pin
as follows:
If the GP43 pin is high, the Device Disable Register is Read-Only.
If the GP43 pin is low, the Device Disable Register is Read/Write.
6.18.2
The Device Disable Register is located in the PME register block at offset 0x22 from the PME_BLK base I/O address
in logical device A. Writes to this register are blocked when the GP43 pin is configured for the Device Disable
Register Control function (GP43 configuration register bit 2 =1) and the GP43 pin is high.
The configuration register for the device disable register is defined in the “Runtime Registers” section.
Device Disable Register
6.19 GAME PORT LOGIC
The LPC47M14x implements logic to support a dual game port. This logic includes the following for each game port:
two 555 timers, two game port RC constant inputs (x-axis and y-axis), two game port button inputs and game port
interface logic. The implementation of the Game Port uses a simple A/D converter constructed from a 555 timer to
digitize the analog value of a potentiometer for the x-axis and y-axis of the joystick.
The figure below illustrates the implementation of the game port logic in the LPC47M14x.
Game software will write a byte to the game port to reset it, and then poll (read) the port until the x and y-axis RC time
constant pins (TIMA,B) time out (return to zero). The elapsed time indicates the resistance value of the potentiometer
and in turn, the position of the joystick.
JOYR
Joystick 1 Button 1
Joystick 1 Button 2
556
OUT1A
OUT1B
TRIG1A
TRIG1B
X-Axis
Y-Axis
TIM1A
TIM1B
JOYW
Vcc = 5V
Internal To LPC47M14x
Joystick 1
D0
D1
D2
D3
D4
D5
D6
D7
556
OUT2A
OUT2B
TRIG2A
TRIG2B
X-Axis
Y-Axis
TIM2A
TIM2B
Vcc = 5V
Joystick 2
Joystick 2 Button 1
Joystick 2 Button 2
J1B1
J1B2
J2B1
J2B2
J1X
J1Y
J2X
J2Y
Game Port
Register
Vcc = 5V
Vcc = 5V
Vcc = 5V
Internal To Joysticks
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LPC47M14W-NC | SNAP LOCK CABLE MARKER - J (10PK) |
| LPC47M14A-NC | 128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M14T-NC | 128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M14S-NC | 128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M192 | LPC SUPER I/O WITH HARDWARE MONITORING BLOCK |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LPC47M14V-NC | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M14W-NC | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M14X | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M14X-NC | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M14Y-NC | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。