參數(shù)資料
型號(hào): LPC47M14G-NC
廠商: SMSC Corporation
英文描述: Electrical Duct/Raceway Fitting;
中文描述: 128引腳ENGANCED超級(jí)I / O與LPC接口和USB集線器控制器
文件頁(yè)數(shù): 13/205頁(yè)
文件大?。?/td> 1219K
代理商: LPC47M14G-NC
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SMSC DS – LPC47M14X
Page 13
Rev. 03/19/2001
QFP
PIN #
NAME
TOTAL
SYMBOL
BUFFER
TYPE
BUFFER TYPE
PER FUNCTION
(NOTE 1)
NOTES
GENERAL PURPOSE I/O (19)
1
GP10 /J1B1
32
General
/Joystick 1 Button 1
General
/Joystick 1 Button 2
General
/Joystick 2 Button 1
General
/Joystick 2 Button 2
General
/Joystick 1 X-Axis
General
/Joystick 1 Y-Axis
General
/Joystick 2 X-Axis
General
/Joystick 2 Y-Axis
General Purpose I/O / P17
General Purpose I/O / P16
/nDS1
General Purpose I/O / P12
/nMTR1
General Purpose I/O /
System Option
General
Purpose
/MIDI_IN
General
Purpose
/MIDI_OUT
General Purpose I/O
/SMI Output
General Purpose I/O /
LED
General Purpose I/O /
LED
General Purpose I/O /
Power Management Event
General Purpose I/O
/Device
Disable
Control
Purpose
I/O
IS/O8
(IS/O8/OD8)/IS
33
Purpose
I/O
1
GP11 /J1B2
IS/O8
(IS/O8/OD8)/IS
34
Purpose
I/O
1
GP12 /J2B1
IS/O8
(IS/O8/OD8)/IS
35
Purpose
I/O
1
GP13 /J2B2
IS/O8
(IS/O8/OD8)/IS
36
Purpose
I/O
1
GP14 /J1X
IO12
(I/O12/OD12)/ IO12
37
Purpose
I/O
1
GP15 /J1Y
IO12
(I/O12/OD12)/ IO12
38
Purpose
I/O
1
GP16 /J2X
IO12
(I/O12/OD12)/ IO12
39
Purpose
I/O
1
GP17 /J2Y
IO12
(I/O12/OD12)/ IO12
41
42
1
1
GP20 /P17
GP21
nDS1
GP22
nMTR1
GP24
/SYSOPT
GP25
/MIDI_IN
GP26
/MIDI_OUT
GP27
/nIO_SMI
GP60 /LED1
IO8
IO12
(I/O8/OD8)/IO8
(I/O12/OD12)/
IO12/(O12/OD12)
(I/O12/OD12)/
IO12/(O12/OD12)
(I/O8/OD8)
/P16/
43
1
/P12/
IO12
45
1
IO8
8
46
I/O
1
IO8
(I/O8/OD8)/I
47
I/O
1
IO12
(I/O12/OD12)/O12
50
1
IO12
(I/O12/OD12)/ OD12
48
1
IO12
(I/O12/OD12)/O12
10
49
1
GP61 /LED2
IO12
(I/O12/OD12)/O12
10
17
1
GP42
/nIO_PME
GP43/DDRC
IO12
(I/O12/OD12)/ OD12
28
Reg.
1
IO8
(I/O8/OD8)/I
Note:
The "n" as the first letter of a signal name or the “#” as the suffix of a signal name indicates an "Active Low"
signal.
Note 1:
Buffer types per function on multiplexed pins are separated by a slash “/”. Buffer types in parenthesis
represent multiple buffer types for a single pin function.
Note 2:
The LPCPD# pin may be tied high. The LPC interface will function properly if the PCI_RESET# signal
follows the protocol defined for the LRESET# signal in the “Low Pin Count Interface Specification”.
Note 3:
For USB Hub functionality, the 32 KHz input clock must always be connected. There is a bit in the
configuration register at 0xF0 in Logical Device A that indicates whether or not the 32KHz clock is
connected. This bit determines the clock source for the fan tachometer, LED and “wake on specific key”
logic. This bit must always be set to ‘0’ (‘0’=32 KHz clock connected; reset default=‘0’).
Note 4:
The fan control pins (FAN1 and FAN2) come up as outputs and low following a VCC POR and Hard Reset.
These pins revert to their non-inverting GPIO
input
function when VCC is removed from the part.
Note 5:
The IRTX pins (IRTX2/GP35 and GP53/TXD2 (IRTX)) are driven low when the part is powered by VTR
(VCC=0V with VTR=3.3V). These pins will remain low following a power-up (VCC POR) until serial port 2
is enabled by setting the activate bit, at which time the pin will reflect the state of the transmit output of the
Serial Port 2 block.
Note 6:
The VCC power-up default for this pin is Logic “0” if the IRTX function is programmed on the GPIO.
Note 7:
VTR must not be connected to VCC. The 32 KHz input clock must not be driven high whenVTR = 0v.
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