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參數(shù)資料
| 型號： | LPC47B27X |
| 廠商： | SMSC Corporation |
| 英文描述： | Round, Jacket Mass-Terminated Cable, 3659/26 28 AWG, .050 (1.27) |
| 中文描述： | 100引腳增強型超的I / O LPC接口控制器 |
| 文件頁數(shù)： | 15/196頁 |
| 文件大小： | 1200K |
| 代理商： | LPC47B27X |
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SMSC LPC47B27x
- 15 -
Rev. 08-10-04
DATASHEET
POWER FUNCTIONALITY
The LPC47B27x has three power planes: VCC, VTR and VREF.
VCC Power
The LPC47B27x is a 3.3 Volt part. The VCC supply is 3.3 Volts (nominal). See the Operational Description Section
and the Maximum Current Values sub-section.
VTR Support
The LPC47B27x requires a trickle supply (V
TR
) to provide sleep current for the programmable wake-up events in the
PME interface when V
CC
is removed. The VTR supply is 3.3 Volts (nominal). See the Operational Description
Section. The maximum VTR current that is required depends on the functions that are used in the part. See Trickle
Power Functionality and Maximum Current Values sub-sections. If the LPC47B27x is not intended to provide wake-
up capabilities on standby current, V
TR
can be connected to V
CC
. V
TR
powers the Consumer IR receiver, IR interface,
the CIR run-time registers, the PME configuration registers, and the PME interface. The V
TR
pin generates a V
TR
Power-on-Reset signal to initialize these components.
Note: If V
TR
is to be used for programmable wake-up events when V
CC
is removed, V
TR
must be at its full minimum
potential at least 10
μ
s before V
cc
begins a power-on cycle. When V
TR
and V
cc
are fully powered, the potential
difference between the two supplies must not exceed 500mV.
Internal PWRGOOD
An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in the host interface
as V
cc
cycles on and off. When the internal PWRGOOD signal is “1” (active), V
cc
> 2.3V (nominal), and the
LPC47B27x host interface is active. When the internal PWRGOOD signal is “0” (inactive), V
cc
≤
2.3V (nominal), and
the LPC47B27x host interface is inactive; that is, LPC bus reads and writes will not be decoded.
The LPC47B27x device pins nIO_PME, CLOCKI32, KDAT, MDAT, IRRX, nRI1, nRI2, RXD2 and most GPIOs (as
input) are part of the PME interface and remain active when the internal PWRGOOD signal has gone inactive,
provided V
TR
is powered. The IRTX2/GP35, GP53/TXD2, GP60/LED1 and GP61/LED2 pins also remain active when
the internal PWRGOOD signal has gone inactive, provided V
TR
is powered. See Trickle Power Functionality section.
The internal PWRGOOD signal is also used to determine the clock source for the CIrCC CIR and to disable the IR
Half Duplex Timeout.
32.768 kHz Trickle Clock Input
The LPC47B27x utilizes a 32.768 kHz trickle input to supply a clock signal for the fan tachometer logic, WDT, LED
blink and wake on specific key function. See the following section for more information.
The LPC47B27x also utilizes the 32.768 kHz trickle clock input and a clock multiplier (PLL) to drive the CIrCC block
when V
cc
has been removed. The PME Power bit, CR22.7, is used to enable (power-up) the 32.768 kHz trickle clock
PLL. When the PME Power bit is set to “1” (active), the 32.768 kHz trickle clock PLL is running and can replace the
14.318 MHz clock source for the CIrCC Wake Event, depending upon the state of the internal PWRGOOD signal.
When the PME Power bit is reset to “0” (inactive/default), the 32.768 kHz trickle clock PLL is unpowered. The PME
power bit does not affect the other wakeup events.
LPC47B27x PLL CONTROLS AND SELECTS
PLL
CONTROL
(CR24.1)
(CR22.7)
PWRGOOD
1
X
X
All PLLs Powered Down
0
0
0
0
0
1
32kHz PLL Unpowered, Not Selected,
14MHz PLL Powered, Selected.
0
1
0
32kHz PLL Powered, Selected,
14MHz PLL Unpowered, Not Selected.
0
1
1
32kHz PLL Powered, Not Selected,
14MHz PLL Powered, Selected.
PME
POWER
INTERNAL
DESCRIPTION
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