參數(shù)資料
型號(hào)： LPC2923FBD100
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： ARM9 microcontroller with CAN, LIN, and USB
中文描述： 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT407-1, LQFP-100
文件頁(yè)數(shù)： 45/84頁(yè)
文件大小： 551K
代理商： LPC2923FBD100
LPC2921_23_25_3
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 14 April 2010
45 of 84
NXP Semiconductors
LPC2921/2923/2925
ARM9 microcontroller with CAN, LIN, and USB
generator. The RDET register keeps track of which clocks are active and inactive, and the
appropriate ‘CLK_SEL’ values are masked and unmasked accordingly. Each clock
detector can also generate interrupts at clock activation and deactivation so that the
system can be notified of a change in internal clock status.
Clock detection is done using a counter running at the
BASE_PCR_CLK
frequency. If no
positive clock edge occurs before the counter has 32 cycles of BASE_PCR_CLK the clock
is assumed to be inactive. As
BASE_PCR_CLK
is slower than any of the clocks to be
detected, normally only one BASE_PCR_CLK cycle is needed to detect activity. After
reset all clocks are assumed to be ‘non-present’, so the RDET status register will be
correct only after 32
BASE_PCR_CLK
cycles.
Note that this mechanism cannot protect against a currently-selected clock going from
active to inactive state. Therefore an inactive clock may still be sent to the system under
special circumstances, although an interrupt can still be generated to notify the system.
Glitch-Free Switching:
Provisions are included in the CGU to allow clocks to be
switched glitch-free, both at the output generator stage and also at secondary source
generators.
In the case of the PLL the clock will be stopped and held low for long enough to allow the
PLL to stabilize and lock before being re-enabled. For all non-PLL Generators the switch
will occur as quickly as possible, although there will always be a period when the clock is
held low due to synchronization requirements.
If the current clock is high and does not go low within 32
cycles of BASE_PCR_CLK
it is
assumed to be inactive and is asynchronously forced low. This prevents deadlocks on the
interface.
6.15.2.2
PLL functional description
A block diagram of the PLL is shown in
Figure 11
. The input clock is fed directly to the
analog section. This block compares the phase and frequency of the inputs and generates
the main clock
2
. These clocks are either divided by 2
×
P by the programmable post
divider to create the output clock, or sent directly to the output. The main output clock is
then divided by M by the programmable feedback divider to generate the feedback clock.
The output signal of the analog section is also monitored by the lock detector to signal
when the PLL has locked onto the input clock.
2.
Generation of the main clock is restricted by the frequency range of the PLL clock input. See
Table 33 “Dynamic characteristics”
.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LPC2923FBD100,551 功能描述:ARM微控制器 - MCU IC ARM9 MCU FLASH 256KB RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT
LPC2925 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:ARM9 microcontroller with CAN, LIN, and USB
LPC2925FBD100 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:ARM9 microcontroller with CAN, LIN, and USB
LPC2925FBD100,551 功能描述:ARM微控制器 - MCU IC ARM9 MCU FLASH 512KB RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT
LPC2926 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:ARM9 microcontroller with CAN, LIN, and USB
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