參數(shù)資料
型號: LPC2923FBD100
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: ARM9 microcontroller with CAN, LIN, and USB
中文描述: 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT407-1, LQFP-100
文件頁數(shù): 30/84頁
文件大?。?/td> 551K
代理商: LPC2923FBD100
LPC2921_23_25_3
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 14 April 2010
30 of 84
NXP Semiconductors
LPC2921/2923/2925
ARM9 microcontroller with CAN, LIN, and USB
6.13.2
LIN
The LPC2921/2923/2925 contain two LIN 2.0 master controllers. These can be used as
dedicated LIN 2.0 master controllers with additional support for sync break generation and
with hardware implementation of the LIN protocol according to spec 2.0.
The key features are:
Complete LIN 2.0 message handling and transfer
One interrupt per LIN message
Slave response time-out detection
Programmable sync-break length
Automatic sync-field and sync-break generation
Programmable inter-byte space
Hardware or software parity generation
Automatic checksum generation
Fault confinement
Fractional baud rate generator
6.13.2.1
Pin description
The two LIN 2.0 master controllers in the LPC2921/2923/2925 have the pins listed below.
The LIN pins are combined with other functions on the port pins of the
LPC2921/2923/2925.
Table 18
shows the LIN pins. For more information see
Ref. 1
subsection 3.43, LIN master controller
.
Table 18.
Symbol
LIN0/1 TXD
LIN0/1 RXD
Remark:
Both LIN channels can be also configured as UART channels.
6.13.3
I
2
C-bus serial I/O controllers
The LPC2921/2923/2925 each contain two I
2
C-bus controllers.
The I
2
C-bus is bidirectional for inter-IC control using only two wires: a Serial CLock line
(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or as a transmitter with
the capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
2
C is a multi-master bus, and it can be
controlled by more than one bus master connected to it.
The main features if the I
2
C-bus interfaces are:
I
2
C0 and I
2
C1 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I
2
C-bus)
and do not support powering off of individual devices connected to the same bus
lines.
Easy to configure as master, slave, or master/slave.
LIN controller pins
Pin name
TXDL0/1
RXDL0/1
Direction
OUT
IN
Description
LIN channel 0/1 transmit data output
LIN channel 0/1 receive data input
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