參數(shù)資料
型號(hào): LPC2888FET180
廠商: NXP SEMICONDUCTORS
元件分類(lèi): 微控制器/微處理器
英文描述: 16/32-bit ARM microcontrollers; 8 kB cache, up to 1 MB flash, Hi-Speed USB 2.0 device, and SDRAM memory interface
中文描述: 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PBGA180
封裝: 10 X 10 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT-640-1, TFBGA-180
文件頁(yè)數(shù): 20/34頁(yè)
文件大?。?/td> 139K
代理商: LPC2888FET180
LPC2880_LPC2888_1
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01 — 22 June 2006
20 of 34
Philips Semiconductors
LPC2880; LPC2888
16/32-bit ARM microcontrollers with external memory interface
An interrupt to the processor can be generated on DMA completion, when a DMA
channel is halfway to completion, or when a DMA error has occurred.
6.13 UART and IrDA
The LPC2880/LPC2888 contains one UART with baud rate generator and IrDA support.
6.13.1
Features
32-B Receive and Transmit FIFOs.
Register locations conform to the 16C650 industry standard.
Receiver FIFO trigger points at 1 B, 16 B, 24 B, and 28 B.
Built-in baud rate generator.
CGU generates UART clock including fractional divider capability.
Auto baud capability.
Optional hardware flow control.
IrDA mode for infrared communication.
6.14 I
2
C-bus interface
The LPC2880/LPC2888 I
2
C-bus interface is byte oriented and has four operating modes:
master Transmit mode, master Receive mode, slave Transmit mode and slave Receive
mode. The interface complies with the entire I
2
C-bus specification, and allows turning
power off to the LPC2880/LPC2888 without causing a problem with other devices on the
same I
2
C-bus.
6.14.1
Features
Standard I
2
C-bus interface, configurable as Master, Slave, or Master/Slave.
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Programmable clock allows adjustment of I
2
C-bus transfer rates.
Bidirectional data transfer between masters and slaves.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
Supports normal (100 kHz) and fast (400 kHz) operation.
6.15 10-bit A/D converter
The LPC2880/LPC2888 contains a single 10-bit successive approximation analog to
digital converter with five multiplexed channels.
6.15.1
Features
10-bit successive approximation analog to digital converter.
Input multiplexing among 5 pins.
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