參數資料
型號: LPC2470FET208
廠商: NXP Semiconductors N.V.
元件分類: 數學處理器
英文描述: Flashless 16-bit-32-bit microcontroller; Ethernet, CAN, LCD, USB 2.0 device-host-OTG, external memory interface
封裝: LPC2470FBD208<SOT459-1 (LQFP208)|<<http://www.nxp.com/packages/SOT459-1.html<1<Always Pb-free,;LPC2470FET208<SOT950-1 (TFBGA208)|<<http://www.nxp.com/packages/SOT950-1.ht
文件頁數: 35/91頁
文件大?。?/td> 747K
代理商: LPC2470FET208
LPC2470
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 8 September 2011
35 of 91
NXP Semiconductors
LPC2470
Flashless 16-bit/32-bit microcontroller
7.11.3
USB OTG controller
USB OTG is a supplement to the
USB 2.0 specification
that augments the capability of
existing mobile devices and USB peripherals by adding host functionality for connection to
USB peripherals.
The OTG controller integrates the host controller, device controller, and a master-only I
2
C
interface to implement OTG dual-role device functionality. The dedicated I
2
C interface
controls an external OTG transceiver.
7.11.3.1
Features
Fully compliant with On-The-Go supplement to the
USB 2.0 Specification, Revision
1.0a
.
Hardware support for Host Negotiation Protocol (HNP).
Includes a programmable timer required for HNP and Session Request Protocol
(SRP).
Supports any OTG transceiver compliant with the
OTG Transceiver Specification
(CEA-2011), Rev. 1.0
.
7.12 CAN controller and acceptance filters
The Controller Area Network (CAN) is a serial communications protocol which efficiently
supports distributed real-time control with a very high level of security. Its domain of
application ranges from high-speed networks to low cost multiplex wiring.
The CAN block is intended to support multiple CAN buses simultaneously, allowing the
device to be used as a gateway, switch, or router between two of CAN buses in industrial
or automotive applications.
Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN
Library block, but the 8-bit registers of those devices have been combined in 32-bit words
to allow simultaneous access in the ARM environment. The main operational difference is
that the recognition of received Identifiers, known in CAN terminology as Acceptance
Filtering, has been removed from the CAN controllers and centralized in a global
Acceptance Filter.
7.12.1
Features
Two CAN controllers and buses.
Data rates to 1 Mbit/s on each bus.
32-bit register and RAM access.
Compatible with
CAN specification 2.0B, ISO 11898-1
.
Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN
buses.
Acceptance Filter can provide FullCAN-style automatic reception for selected
Standard Identifiers.
FullCAN messages can generate interrupts.
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