參數(shù)資料
型號: LPC2470FET208
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: Flashless 16-bit-32-bit microcontroller; Ethernet, CAN, LCD, USB 2.0 device-host-OTG, external memory interface
封裝: LPC2470FBD208<SOT459-1 (LQFP208)|<<http://www.nxp.com/packages/SOT459-1.html<1<Always Pb-free,;LPC2470FET208<SOT950-1 (TFBGA208)|<<http://www.nxp.com/packages/SOT950-1.ht
文件頁數(shù): 24/91頁
文件大?。?/td> 747K
代理商: LPC2470FET208
LPC2470
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 8 September 2011
24 of 91
NXP Semiconductors
LPC2470
Flashless 16-bit/32-bit microcontroller
DBGEN
9
[1][16]
F4
[1][16]
I
DBGEN —
JTAG interface control signal. Also used for boundary
scanning.
TDO —
Test Data Out for JTAG interface.
TDI —
Test Data In for JTAG interface.
TMS —
Test Mode Select for JTAG interface.
TRST —
Test Reset for JTAG interface.
TCK —
Test Clock for JTAG interface. This clock must be slower than
1
6
of the CPU clock (CCLK) for the JTAG interface to operate.
RTCK —
JTAG interface control signal.
Note:
LOW on this pin while RESET is LOW enables ETM pins (P2[9:0])
to operate as Trace port after reset.
RSTOUT —
This is a 3.3 V pin. LOW on this pin indicates LPC2470
being in Reset state.
external reset input:
A LOW on this pin resets the device, causing I/O
ports and peripherals to take on their default states, and processor
execution to begin at address 0. TTL with hysteresis, 5 V tolerant.
Input to the oscillator circuit and internal clock generator circuits.
Output from the oscillator amplifier.
Input to the RTC oscillator circuit.
Output from the RTC oscillator circuit.
ground:
0 V reference for the digital IO pins.
TDO
TDI
TMS
TRST
TCK
2
[1][17]
4
[1][16]
6
[1][16]
8
[1][16]
10
[1][17]
D3
[1][17]
C2
[1][16]
E3
[1][16]
D1
[1][16]
E2
[1][17]
O
I
I
I
I
RTCK
206
[1][16]
C3
[1][16]
I/O
RSTOUT
29
K3
O
RESET
35
[12]
M2
[12]
I
XTAL1
XTAL2
RTCX1
RTCX2
V
SSIO
44
[13][14]
46
[13][14]
34
[13][15]
36
[13][15]
33, 63,
77, 93,
114,
133,
148,
169,
189,
200
[13]
32, 84,
172
[13]
22
[13]
M4
[13][14]
I
N4
[13][14]
O
K2
[13][15]
L2
[13][15]
L3, T5,
R9, P12,
N16,
H14,
E15,
A12, B6,
A2
[13]
I
O
I
V
SSCORE
K4, P10,
D12
[13]
J2
[13]
I
ground:
0 V reference for the core.
V
SSA
I
analog ground:
0 V reference. This should nominally be the same
voltage as V
SSIO
/V
SSCORE
, but should be isolated to minimize noise and
error.
3.3 V supply voltage:
This is the power supply voltage for the I/O ports.
V
DD(3V3)
15, 60,
71, 89,
112,
125,
146,
165,
181,
198
[13]
30, 117,
141
[13]
26, 86,
174
[13]
20
[13]
G3, P6,
P8, U13,
P17,
K16,
C17,
B13, C9,
D7
[13]
I
n.c.
J4, L14,
G14
[13]
H4, P11,
D11
[13]
G4
[13]
I
not connected pins:
These pins must be left unconnected (floating).
V
DD(DCDC)(3V3)
I
3.3 V DC-to-DC converter supply voltage:
This is the power supply for
the on-chip DC-to-DC converter.
analog 3.3 V pad supply voltage:
This should be nominally the same
voltage as V
DD(3V3)
but should be isolated to minimize noise and error.
This voltage is used to power the ADC and DAC.
V
DDA
I
Table 4.
Symbol
Pin description
…continued
Pin
Ball
Type
Description
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