參數(shù)資料
型號(hào): LPC2468FET208
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: Single-chip 16-bit-32-bit micro; 512 kB flash, Ethernet, CAN, ISP-IAP, USB 2.0 device-host-OTG, external memory interface
封裝: LPC2468FBD208<SOT459-1 (LQFP208)|<<http://www.nxp.com/packages/SOT459-1.html<1<Always Pb-free,;LPC2468FET208<SOT950-1 (TFBGA208)|<<http://www.nxp.com/packages/SOT950-1.ht
文件頁(yè)數(shù): 22/85頁(yè)
文件大?。?/td> 682K
代理商: LPC2468FET208
LPC2468
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6.1 — 6 September 2011
22 of 85
NXP Semiconductors
LPC2468
Single-chip 16-bit/32-bit micro
P4[29]/BLS3/
MAT2[1]/RXD3
176
[1]
B10
[1]
I/O
O
O
I
I/O
O
I/O
O
O
P4[29] —
General purpose digital input/output pin.
BLS3 —
LOW active Byte Lane select signal 3.
MAT2[1] —
Match output for Timer 2, channel 1.
RXD3 —
Receiver input for UART3.
P4[30] —
General purpose digital input/output pin.
CS0 —
LOW active Chip Select 0 signal.
P4[31] —
General purpose digital input/output pin.
CS1 —
LOW active Chip Select 1 signal.
ALARM —
RTC controlled output. This is a 1.8 V pin. It goes HIGH when
a RTC alarm is generated.
USB_D
2 —
USB port 2 bidirectional D
line.
DBGEN —
JTAG interface control signal. Also used for boundary
scanning.
TDO —
Test Data Out for JTAG interface.
TDI —
Test Data In for JTAG interface.
TMS —
Test Mode Select for JTAG interface.
TRST —
Test Reset for JTAG interface.
TCK —
Test Clock for JTAG interface. This clock must be slower than
1
6
of the CPU clock (CCLK) for the JTAG interface to operate.
P4[30]/CS0
187
[1]
B7
[1]
P4[31]/CS1
193
[1]
A4
[1]
ALARM
37
[7]
N1
[7]
USB_D
2
DBGEN
52
9
[1][8]
U1
F4
[1][8]
I/O
I
TDO
TDI
TMS
TRST
TCK
2
[1][9]
4
[1][8]
6
[1][8]
8
[1][8]
10
[1][9]
D3
[1][9]
C2
[1][8]
E3
[1][8]
D1
[1][8]
E2
[1][9]
O
I
I
I
I
RTCK
206
[1][8]
C3
[1][8]
I/O
RTCK —
JTAG interface control signal.
Note:
LOW on this pin while RESET is LOW enables ETM pins (P2[9:0])
to operate as Trace port after reset.
RSTOUT —
This is a 3.3 V pin. LOW on this pin indicates LPC2468
being in Reset state.
external reset input:
A LOW on this pin resets the device, causing I/O
ports and peripherals to take on their default states, and processor
execution to begin at address 0. TTL with hysteresis, 5 V tolerant.
Input to the oscillator circuit and internal clock generator circuits.
Output from the oscillator amplifier.
Input to the RTC oscillator circuit.
Output from the RTC oscillator circuit.
ground:
0 V reference for the digital I/O pins.
RSTOUT
29
[1]
K3
[1]
O
RESET
35
[10]
M2
[10]
I
XTAL1
XTAL2
RTCX1
RTCX2
V
SSIO
44
[7][11]
46
[7][11]
34
[7][12]
36
[7][12]
33, 63,
77, 93,
114,
133,
148,
169,
189,
200
[13]
32, 84,
172
[13]
22
[14]
M4
[7][11]
N4
[7][11]
K2
[7][12]
L2
[7][12]
L3, T5,
R9, P12,
N16,
H14,
E15,
A12, B6,
A2
[13]
I
O
I
O
I
V
SSCORE
K4, P10,
D12
[13]
J2
[14]
I
ground:
0 V reference for the core.
V
SSA
I
analog ground:
0 V reference. This should nominally be the same
voltage as V
SSIO
/V
SSCORE
, but should be isolated to minimize noise and
error.
Table 4.
Symbol
Pin description
…continued
Pin
Ball
Type
Description
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