- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385497 > LPC2362FBD100 (NXP Semiconductors N.V.) Single-chip 16-bit-32-bit MCU; up to 128 kB flash with ISP-IAP, Ethernet, USB 2.0 device-host-OTG, CAN, and 10-bit ADC-DAC PDF資料下載
參數(shù)資料
| 型號： | LPC2362FBD100 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 數(shù)學處理器 |
| 英文描述： | Single-chip 16-bit-32-bit MCU; up to 128 kB flash with ISP-IAP, Ethernet, USB 2.0 device-host-OTG, CAN, and 10-bit ADC-DAC |
| 封裝： | LPC2361FBD100<SOT407-1 (LQFP100)|<<http://www.nxp.com/packages/SOT407-1.html<1<Always Pb-free,;LPC2362FBD100<SOT407-1 (LQFP100)|<<http://www.nxp.com/packages/SOT407-1.htm |
| 文件頁數(shù)： | 31/64頁 |
| 文件大小： | 475K |
| 代理商： | LPC2362FBD100 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
LPC2361_62
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 25 October 2011
31 of 64
NXP Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit MCU
7.24.2
Brownout detection
The LPC2361/2362 includes 2-stage monitoring of the voltage on the V
DD(DCDC)(3V3)
pins.
If this voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored
Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable
Register in the VIC in order to cause a CPU interrupt; if not, software can monitor the
signal by reading a dedicated status register.
The second stage of low-voltage detection asserts Reset to inactivate the LPC2361/2362
when the voltage on the V
DD(DCDC)(3V3)
pins falls below 2.65 V. This Reset prevents
alteration of the flash as operation of the various elements of the chip would otherwise
become unreliable due to low voltage. The BOD circuit maintains this reset down below
1 V, at which point the power-on reset circuitry maintains the overall Reset.
Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this
hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly executed event
loop to sense the condition.
7.24.3
Code security (Code Read Protection - CRP)
This feature of the LPC2361/2362 allows user to enable different levels of security in the
system so that access to the on-chip flash and use of the JTAG and ISP can be restricted.
When needed, CRP is invoked by programming a specific pattern into a dedicated flash
location. IAP commands are not affected by the CRP.
There are three levels of the Code Read Protection.
CRP1 disables access to chip via the JTAG and allows partial flash update (excluding
flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is
required and flash field updates are needed but all sectors can not be erased.
CRP2 disables access to chip via the JTAG and only allows full flash erase and update
using a reduced set of the ISP commands.
Running an application with level CRP3 selected fully disables any access to chip via the
JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too.
It is up to the user’s application to provide (if needed) flash update mechanism using IAP
calls or call reinvoke ISP command to enable flash update via UART0.
7.24.4
AHB
The LPC2362 implements two AHBs in order to allow the Ethernet block to operate
without interference caused by other system activity. The primary AHB, referred to as
AHB1, includes the Vectored Interrupt Controller, GPDMA controller, USB interface, and
8 kB SRAM primarily intended for use by the USB.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
相關PDF資料 |
PDF描述 |
|---|---|
| LPC2364FBD100 | ARM7 with 128 kB flash, 34 kB SRAM, Ethernet, USB 2.0 Device, CAN, and 10-bit ADC |
| LPC2365FBD100 | ARM7 with 256 kB flash, 58 kB SRAM, Ethernet and 10-bit ADC |
| LPC2366FBD100 | ARM7 with 256 kB flash, 58 kB SRAM, Ethernet, USB 2.0 Device, CAN, and 10-bit ADC |
| LPC2367FBD100 | ARM7 with 512 kB flash, 58 kB SRAM, Ethernet and 10-bit ADC |
| LPC2368FBD100 | ARM7 with 512 kB flash, 58 kB SRAM, Ethernet, USB 2.0 Device, CAN, SD-MMC, and 10-bit ADC |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LPC2362FBD100,551 | 功能描述:ARM微控制器 - MCU 128K FL/ ETH USB OTG CAN RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
| LPC2364 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC |
| LPC2364_10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC |
| LPC2364FB100 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC |
| LPC2364FBD100 | 制造商:NXP Semiconductors 功能描述:MCU 32BIT ARM7 10/100 USB CAN 制造商:NXP Semiconductors 功能描述:MCU 32BIT ARM7, 10/100, USB, CAN 制造商:NXP Semiconductors 功能描述:IC, 32BIT MCU, ARM7, 72MHZ, LQFP-100; Controller Family/Series:(ARM7); Core Size:32bit; No. of I/O's:70; Supply Voltage Min:3V; Supply Voltage Max:3.6V; Digital IC Case Style:LQFP; No. of Pins:100; Program Memory Size:128KB ;RoHS Compliant: Yes 制造商:NXP Semiconductors 功能描述:Microcontroller,LPC2364FBD100 72 MHz |
發(fā)布緊急采購，3分鐘左右您將得到回復。