參數(shù)資料
型號: LPC2361FBD100
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學處理器
英文描述: Single-chip 16-bit-32-bit MCU; up to 128 kB flash with ISP-IAP, Ethernet, USB 2.0 device-host-OTG, CAN, and 10-bit ADC-DAC
封裝: LPC2361FBD100<SOT407-1 (LQFP100)|<<http://www.nxp.com/packages/SOT407-1.html<1<Always Pb-free,;LPC2362FBD100<SOT407-1 (LQFP100)|<<http://www.nxp.com/packages/SOT407-1.htm
文件頁數(shù): 21/64頁
文件大小: 475K
代理商: LPC2361FBD100
LPC2361_62
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 25 October 2011
21 of 64
NXP Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit MCU
Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN
Library block, but the 8-bit registers of those devices have been combined in 32-bit words
to allow simultaneous access in the ARM environment. The main operational difference is
that the recognition of received Identifiers, known in CAN terminology as Acceptance
Filtering, has been removed from the CAN controllers and centralized in a global
Acceptance Filter.
7.11.1
Features
Two CAN controllers and buses.
Data rates to 1 Mbit/s on each bus.
32-bit register and RAM access.
Compatible with
CAN specification 2.0B, ISO 11898-1
.
Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN
buses.
Acceptance Filter can provide FullCAN-style automatic reception for selected
Standard Identifiers.
FullCAN messages can generate interrupts.
7.12 10-bit ADC
The LPC2361/2362 contain one ADC. It is a single 10-bit successive approximation ADC
with six channels.
7.12.1
Features
10-bit successive approximation ADC.
Input multiplexing among 6 pins.
Power-down mode.
Measurement range 0 V to V
i(VREF)
.
10-bit conversion time
2.44
s.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition of input pin or Timer Match signal.
Individual result registers for each ADC channel to reduce interrupt overhead.
7.13 10-bit DAC
The DAC allows the LPC2361/2362 to generate a variable analog output. The maximum
output value of the DAC is V
i(VREF)
.
7.13.1
Features
10-bit DAC
Resistor string architecture
Buffered output
Power-down mode
Selectable output drive
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