參數(shù)資料
型號(hào): LPC2106FBD48,151
廠商: NXP Semiconductors
文件頁數(shù): 8/41頁
文件大?。?/td> 0K
描述: IC ARM7 MCU FLASH 128K 48-LQFP
標(biāo)準(zhǔn)包裝: 250
系列: LPC2100
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 60MHz
連通性: I²C,Microwire,SPI,SSI,SSP,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 128KB(128K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-LQFP
包裝: 托盤
配用: 622-1019-ND - BOARD FOR LPC2106 48-LQFP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
568-1756-ND - BOARD EVAL FOR LPC210X ARM MCU
其它名稱: 568-1890
935275298151
LPC2106FBD48-S
LPC2104_2105_2106_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 20 June 2008
16 of 41
NXP Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
6.9 General purpose parallel I/O
Device pins that are not connected to a specic peripheral function are controlled by the
GPIO registers. Pins may be dynamically congured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back, as well as the current state of the port pins.
6.9.1 Features
Direction control of individual bits.
Separate control of output set and clear.
All I/O default to inputs after reset.
6.9.2 Features added with the Fast GPIO set of registers available on
LPC2104/2105/2106/01 only
Fast GPIO registers are relocated to the ARM local bus for the fastest possible I/O
timing, enabling port pin toggling up to 3.5 times faster than earlier LPC2000 devices.
Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
All Fast GPIO registers are byte addressable.
Entire port value can be written in one instruction.
Ports are accessible via either the legacy group of registers (GPIOs) or the group of
registers providing accelerated port access (Fast GPIOs).
6.10 UARTs
The LPC2104/2105/2106 each contain two UARTs. One UART provides a full modem
control handshake interface, the other provides only transmit and receive data lines.
6.10.1 Features
16 byte Receive and Transmit FIFOs
Register locations conform to 16C550 industry standard
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B
Built-in baud rate generator
25:24
P0.28
0
GPIO Port 0.28
0
1
TMS
27:26
P0.29
0
GPIO Port 0.29
0
1
TCK
29:28
P0.30
0
GPIO Port 0.30
0
1
TDI
31:30
P0.31
0
GPIO Port 0.31
0
1
TDO
Table 7.
Pin function select register 1 (PINSEL1 - 0xE002 C004) …continued
PINSEL1
Pin name
Value
Function
Value after
reset
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