參數(shù)資料
型號: LPC2103
廠商: NXP Semiconductors N.V.
英文描述: Single-chip 16-bit/32-bit microcontrollers; 8 kB/16 kB/32 kB flash with ISP/IAP, fast ports and 10-bit ADC
中文描述: 單芯片16-bit/32-bit微控制器; 8 kB/16 kB/32具有ISP /聯(lián)合會(huì),快速端口和10位ADC kB閃存
文件頁數(shù): 8/32頁
文件大?。?/td> 128K
代理商: LPC2103
LPC2101_02_03_1
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01 — 18 January 2006
8 of 32
Philips Semiconductors
LPC2101/2102/2103
Single-chip 16-bit/32-bit microcontrollers
P0.21/SSEL1/
MAT3.0
3
[4]
9
[4]
I/O
I
P0.21 —
General purpose Input/output digital pin (GPIO).
SSEL1 —
Slave Select for SPI1. Selects the SPI interface as
a slave.
MAT3.0 —
PWM output for Timer 3, channel 0.
P0.22 —
General purpose Input/output digital pin (GPIO).
AD0.0 —
ADC 0, input 0.
P0.23 —
General purpose Input/output digital pin (GPIO).
AD0.1 —
ADC 0, input 1.
P0.24 —
General purpose Input/output digital pin (GPIO).
AD0.2 —
ADC 0, input 2.
P0.25 —
General purpose Input/output digital pin (GPIO).
AD0.6 —
ADC 0, input 6.
P0.26 —
General purpose Input/output digital pin (GPIO).
AD0.7 —
ADC 0, input 7.
P0.27 —
General purpose Input/output digital pin (GPIO).
TRST —
Test Reset for JTAG interface.
CAP2.0 —
Capture input for Timer 2, channel 0.
P0.28 —
General purpose Input/output digital pin (GPIO).
TMS —
Test Mode Select for JTAG interface.
CAP2.1 —
Capture input for Timer 2, channel 1.
P0.29 —
General purpose Input/output digital pin (GPIO).
TCK —
Test Clock for JTAG interface.
CAP2.2 —
Capture input for Timer 2, channel 2.
P0.30 —
General purpose Input/output digital pin (GPIO).
TDI —
Test Data In for JTAG interface.
MAT3.3 —
PWM output 3 for Timer 3.
P0.31 —
General purpose output only digital pin (GPIO).
TDO —
Test Data Out for JTAG interface.
Input to the RTC oscillator circuit.
Output from the RTC oscillator circuit.
Returned test clock output:
Extra signal added to the JTAG
port. Assists debugger synchronization when processor
frequency varies. Bidirectional pin with internal pull-up.
Input to the oscillator circuit and internal clock generator
circuits.
Output from the oscillator amplifier.
Debug select:
When LOW, the part operates normally. When
HIGH, debug mode is entered. Input with internal pull-down.
External reset input:
A LOW on this pin resets the device,
causing I/O ports and peripherals to take on their default
states and processor execution to begin at address 0. TTL
with hysteresis, 5 V tolerant.
Ground:
0 V reference.
O
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I
I/O
I
I
I/O
I
I
I/O
I
O
O
O
I
O
I/O
P0.22/AD0.0
32
[4]
35
[4]
P0.23/AD0.1
33
[1]
36
[1]
P0.24/AD0.2
34
[1]
37
[1]
P0.25/AD0.6
38
[1]
41
[1]
P0.26/AD0.7
39
[1]
n.c.
P0.27/TRST/
CAP2.0
8
[4]
13
[4]
P0.28/TMS/
CAP2.1
9
[4]
14
[4]
P0.29/TCK/
CAP2.2
10
[4]
15
[4]
P0.30/TDI/
MAT3.3
15
[4]
20
[4]
P0.31/TDO
16
[4]
21
[4]
RTXC1
RTXC2
RTCK
20
[5]
25
[5]
26
[5]
24
[5]
29
[5]
n.c.
X1
11
16
I
X2
DBGSEL
12
27
17
30
O
I
RST
6
11
I
V
SS
7, 19, 43
1, 12, 23
I
Table 3:
Symbol
Pin description
…continued
LQFP48
PLCC44
Type
Description
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