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| 型號： | LPC2103 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Single-chip 16-bit/32-bit microcontrollers; 8 kB/16 kB/32 kB flash with ISP/IAP, fast ports and 10-bit ADC |
| 中文描述： | 單芯片16-bit/32-bit微控制器; 8 kB/16 kB/32具有ISP /聯(lián)合會，快速端口和10位ADC kB閃存 |
| 文件頁數(shù)： | 14/32頁 |
| 文件大小： | 128K |
| 代理商： | LPC2103 |
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LPC2101_02_03_1
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01 — 18 January 2006
14 of 32
Philips Semiconductors
LPC2101/2102/2103
Single-chip 16-bit/32-bit microcontrollers
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
Transmission FIFO control enables implementation of software (XON/XOFF) flow
control on both UARTs.
UART1 is equipped with standard modem interface signals. This module also
provides full support for hardware flow control (auto-CTS/RTS).
6.10 I
2
C-bus serial I/O controllers
The LPC2101/2102/2103 each contain two I
2
C-bus controllers.
The I
2
C-bus is bidirectional, for inter-IC control using only two wires: a Serial Clock Line
(SCL), and a Serial Data Line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., LCD driver) or a transmitter with the
capability to both receive and send information such as serial memory. Transmitters
and/or receivers can operate in either master or slave mode, depending on whether the
chip has to initiate a data transfer or is only addressed. The I
2
C-bus is a multi-master bus,
it can be controlled by more than one bus master connected to it.
The I
2
C-bus implemented in LPC2101/2102/2103 supports bit rates up to 400 kbit/s (Fast
I
2
C).
6.10.1
Features
Compliant with standard I
2
C-bus interface.
Easy to configure as Master, Slave, or Master/Slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
2
C-bus can also be used for test and diagnostic purposes.
6.11 SPI serial I/O controller
The LPC2101/2102/2103 each contain one SPI controller. The SPI is a full duplex serial
interface, designed to handle multiple masters and slaves connected to a given bus. Only
a single master and a single slave can communicate on the interface during a given data
transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the
slave, and the slave always sends 8 bits to 16 bits of data to the master.
6.11.1
Features
Compliant with SPI specification.
Synchronous, Serial, Full Duplex, Communication.
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| LPC2103FBD48,151 | 功能描述:ARM微控制器 - MCU ARM7 32KF/8KR/10BADC RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LPC2103FBD48.151 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single-chip 16-bit/32-bit microcontrollers; 8 kB/16 kB/32 kB flash with ISP/IAP, fast ports and 10-bit ADC |
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